Abstract: A comparator with a latch circuit includes a comparator circuit and a latch circuit. The comparator circuit includes first to third transistor pairs constituting differential pairs. The first transistor pair, which receives a clock in a conventional circuit, receives input data. The bases of the second and third transistor pairs receive a clock. The collector of one transistor of each of the second and third transistor pairs is connected to a power source through a load resistor. The latch circuit includes fourth to sixth transistor pairs constituting differential pairs. The fourth transistor pair receives at their bases the collector potentials, having the load resistances, of the second and third transistor pairs through emitter-follower circuits. The fifth and sixth transistor pairs receive clocks having opposite polarities at their bases. The collector of one transistor of each of the fifth and sixth transistor pairs is connected to the corresponding load resistor.