Abstract: A filter circuit includes two parallel digital filters, a DAC, and an LPF. The DAC includes two parallel decoders, a parallel-to-serial converter, a switch driver, and a switch. A PLL circuit supplies a reference clock to the DAC. A frequency divider provided in the DAC divides the frequency of the reference clock by two, and supplies the half frequency clock to a parallel processing section (the two decoders and the parallel-to-serial converter) of the DAC and the two digital filters. This makes it easy to secure a timing margin, permitting use in high-speed communication on the order of several GHz.

Abstract: A filter circuit includes two parallel digital filters, a DAC, and an LPF. The DAC includes two parallel decoders, a parallel-to-serial converter, a switch driver, and a switch. A PLL circuit supplies a reference clock to the DAC. A frequency divider provided in the DAC divides the frequency of the reference clock by two, and supplies the half frequency clock to a parallel processing section (the two decoders and the parallel-to-serial converter) of the DAC and the two digital filters. This makes it easy to secure a timing margin, permitting use in high-speed communication on the order of several GHz.

Abstract: A filter circuit includes two parallel digital filters, a DAC, and an LPF. The DAC includes two parallel decoders, a parallel-to-serial converter, a switch driver, and a switch. A PLL circuit supplies a reference clock to the DAC. A frequency divider provided in the DAC divides the frequency of the reference clock by two, and supplies the half frequency clock to a parallel processing section (the two decoders and the parallel-to-serial converter) of the DAC and the two digital filters. This makes it easy to secure a timing margin, permitting use in high-speed communication on the order of several GHz.

Abstract: When a semiconductor circuit, in which a stabilizing capacitor 2 for stabilizing a reference voltage Vbias is connected to a reference voltage terminal RT, recovers from a power down state to an operational state, a current mirror circuit 40 provides current mirroring of a current Ia of a first current path Ph1, which generates an OFF threshold voltage ref1 of a hysteresis comparator 1, to generate a current Ib of a second current path Ph2, which generates the reference voltage Vbias. The reference voltage Vbias is input to the comparator 1 as an input voltage vin. When the reference voltage Vbias becomes equal to the OFF threshold voltage ref1, the comparator 1 immediately stops the charging of the stabilizing capacitor 2 by a current source I1.

Abstract: In a multi-channel current steering DA converter, e.g., a two-channel current steering DA converter, reference current sources Irefa and Irefb that can serve as current mirror sources for current sources Ia and Ib are provided in current source matrices 2a and 2b of the channels, respectively. During an operation, the reference current source Irefa or Irefb that is provided in the current source matrix of a channel that is not powered down is selected and used in accordance with control signals 6a and 6b. Therefore, even when one channel is powered down, the full-scale current of the other channel can be maintained at a constant value, i.e., unchanged.

Abstract: In a multiple signal switching circuit using four input signals IN1-IN4, a four-input latch circuit 3b is located. Four NAND circuits 6? are used as the four-input latch circuit 3b, when one of the four signals IN1-IN4 is “L” and the other three are “H.” In each of the NAND circuits 6?, an output is coupled to one of the four input signals IN1-IN4, the three signals other than the coupled signal are coupled to inputs. Therefore, even in a multiple signal switching circuit having three or more input signals, timing errors among multiple signals to be output can be effectively reduced.

Abstract: In a multi-channel current steering DA converter, e.g., a two-channel current steering DA converter, reference current sources Irefa and Irefb that can serve as current mirror sources for current sources Ia and Ib are provided in current source matrices 2a and 2b of the channels, respectively. During an operation, the reference current source Irefa or Irefb that is provided in the current source matrix of a channel that is not powered down is selected and used in accordance with control signals 6a and 6b. Therefore, even when one channel is powered down, the full-scale current of the other channel can be maintained at a constant value, i.e., unchanged.

Abstract: In a multi-channel current steering DA converter, e.g., a two-channel current steering DA converter, reference current sources Irefa and Irefb that can serve as current mirror sources for current sources Ia and Ib are provided in current source matrices 2a and 2b of the channels, respectively. During an operation, the reference current source Irefa or Irefb that is provided in the current source matrix of a channel that is not powered down is selected and used in accordance with control signals 6a and 6b. Therefore, even when one channel is powered down, the full-scale current of the other channel can be maintained at a constant value, i.e., unchanged.

Abstract: A standard voltage generation circuit is provided with a function of automatically stopping charging when a standard voltage reaches a stable voltage point by rapidly charging a standard voltage stabilization capacitor during transition from a standby state to a normal operation state. The standard voltage generation circuit is also provided with a function of precharging an output terminal of the circuit to a voltage close to the stable voltage by a potential division effect of the capacitor during transition from the standby state to the normal operation state. Thereby, it is possible to prevent an increase in the amount of time that is required until the standard voltage reaches the stable voltage when the state of an analog circuit included in the standard voltage generation circuit changes from its off state to its on state.

Abstract: A multi-channel current steering DAC (Digital-to-Analog Converter), for example, a 2-channel current steering DAC, includes a plurality of current sources I1, I2, . . . corresponding to the number of bits of a digital input signal DS in each of channels A, B. Each of the plurality of current sources I1, I2, . . . is formed by two small-current sources (I11, I12), (I21, I22), . . . . In the case where a full-scale current is limited to a small value in any of the channels, one of the two divided current sources is turned off by switches Sa1, Sa2. Accordingly, a full-scale current of each channel can be adjusted with a common bias circuit without degrading the resolution.

Abstract: When a semiconductor circuit, in which a stabilizing capacitor 2 for stabilizing a reference voltage Vbias is connected to a reference voltage terminal RT, recovers from a power down state to an operational state, a current mirror circuit 40 provides current mirroring of a current Ia of a first current path Ph1, which generates an OFF threshold voltage ref1 of a hysteresis comparator 1, to generate a current Ib of a second current path Ph2, which generates the reference voltage Vbias. The reference voltage Vbias is input to the comparator 1 as an input voltage vin. When the reference voltage Vbias becomes equal to the OFF threshold voltage ref1, the comparator 1 immediately stops the charging of the stabilizing capacitor 2 by a current source I1.

Abstract: In a multi-channel current steering DA converter, e.g., a two-channel current steering DA converter, reference current sources Irefa and Irefb that can serve as current mirror sources for current sources Ia and Ib are provided in current source matrices 2a and 2b of the channels, respectively. During an operation, the reference current source Irefa or Irefb that is provided in the current source matrix of a channel that is not powered down is selected and used in accordance with control signals 6a and 6b. Therefore, even when one channel is powered down, the full-scale current of the other channel can be maintained at a constant value, i.e., unchanged.

Abstract: A multi-channel current steering DAC (Digital-to-Analog Converter), for example, a 2-channel current steering DAC, includes a plurality of current sources I1, I2, . . . corresponding to the number of bits of a digital input signal DS in each of channels A, B. Each of the plurality of current sources I1, I2, . . . is formed by two small-current sources (I11, I12), (I21, I22), . . . . In the case where a full-scale current is limited to a small value in any of the channels, one of the two divided current sources is turned off by switches Sa1, Sa2. Accordingly, a full-scale current of each channel can be adjusted with a common bias circuit without degrading the resolution.

Abstract: A standard voltage generation circuit is provided with a function of automatically stopping charging when a standard voltage reaches a stable voltage point by rapidly charging a standard voltage stabilization capacitor during transition from a standby state to a normal operation state. The standard voltage generation circuit is also provided with a function of precharging an output terminal of the circuit to a voltage close to the stable voltage by a potential division effect of the capacitor during transition from the standby state to the normal operation state. Thereby, it is possible to prevent an increase in the amount of time that is required until the standard voltage reaches the stable voltage when the state of an analog circuit included in the standard voltage generation circuit changes from its off state to its on state.

Abstract: A standard voltage generation circuit is provided with a function of automatically stopping charging when a standard voltage reaches a stable voltage point by rapidly charging a standard voltage stabilization capacitor during transition from a standby state to a normal operation state. The standard voltage generation circuit is also provided with a function of precharging an output terminal of the circuit to a voltage close to the stable voltage by a potential division effect of the capacitor during transition from the standby state to the normal operation state. Thereby, it is possible to prevent an increase in the amount of time that is required until the standard voltage reaches the stable voltage when the state of an analog circuit included in the standard voltage generation circuit changes from its off state to its on state.

Abstract: A standard voltage generation circuit is provided with a function of automatically stopping charging when a standard voltage reaches a stable voltage point by rapidly charging a standard voltage stabilization capacitor during transition from a standby state to a normal operation state. Further, the standard voltage generation circuit is provided with a function of precharging an output terminal of the circuit to a voltage close to the stable voltage by a potential division effect of the capacitor during transition from the standby state to the normal operation state. Thereby, it is possible to prevent an increase in time required until the standard voltage reaches the stable voltage when the standard voltage generation circuit including an analog circuit changes from its off state to its on state.