Patents by Inventor Michimasa Funabashi
Michimasa Funabashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20180254201Abstract: A single-wafer substrate processing device is provided which does not spill a processing liquid and the vapors thereof to an exterior when directly supplying the process liquid to a surface of a substrate to process the substrate and which prevents the process liquid and the vapors, etc., thereof to adhere a ceiling, etc., of a housing. The device includes a housing 1, holding means 4 that holds, in the housing 1, a substrate 3 subjected to an eliminating process of adhering materials on a processing surface with a processing surface 3a being directed to the bottom 1b of the housing, supply means that supplies a process liquid to the processing surface 3a of the substrate 3 held by the holding means 4, an inlet 1a for taking in a gaseous body in the housing 1, and an outlet 1c for evacuating from the housing the vapors of the process liquid in the housing 1 together with the gaseous body taken in from the inlet 1a.Type: ApplicationFiled: May 2, 2018Publication date: September 6, 2018Inventors: Michimasa FUNABASHI, Kenji OTOKUNI, Hiroki EDO, Hideaki SUZUKI
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Publication number: 20120257181Abstract: A single-wafer substrate processing device is provided which does not spill a processing liquid and the vapors thereof to an exterior when directly supplying the process liquid to a surface of a substrate to process the substrate and which prevents the process liquid and the vapors, etc., thereof to adhere a ceiling, etc., of a housing. The device includes a housing 1, holding means 4 that holds, in the housing 1, a substrate 3 subjected to an eliminating process of adhering materials on a processing surface with a processing surface 3a being directed to the bottom 1b of the housing, supply means that supplies a process liquid to the processing surface 3a of the substrate 3 held by the holding means 4, an inlet 1a for taking in a gaseous body in the housing 1, and an outlet 1c for evacuating from the housing the vapors of the process liquid in the housing 1 together with the gaseous body taken in from the inlet 1a.Type: ApplicationFiled: December 13, 2010Publication date: October 11, 2012Inventors: Michimasa Funabashi, Kenji Otokuni, Hiroki Edo, Hideaki Suzuki
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Publication number: 20050274694Abstract: A semiconductor manufacturing apparatus capable of removing metal derived from an electrode from ozone generated by the silent discharge is provided. The ozone generated by the silent discharge between electrodes in the ozone generating unit is permeated through a molecule permeable film based on pressure difference between the back and the front of the molecule permeable film constituting a filter. The permeated ozone is supplied together with separately-generated water vapor to a resist surface on a semiconductor wafer to remove the resist. In the resist removal described above, the high-concentration metal contamination due to the metal derived from an electrode can be prevented.Type: ApplicationFiled: June 9, 2005Publication date: December 15, 2005Inventors: Michimasa Funabashi, Shigeru Omata, Nobuaki Toma, Masatoshi Fukushima
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Publication number: 20050233554Abstract: The present invention provides a technology for suppressing occurrence of abnormality on a surface of a silicon film other than a single crystal film formed on a wafer. A silicon film is formed on a wafer in step S1 and an oxide film functioning as an abnormality suppression film for suppressing the surface abnormality is formed on the silicon surface on the wafer formed in step S10. The abnormality suppression film is formed by the surface oxidation of the polycrystalline silicon using chemical solution such as ozone water or hydrogen peroxide solution. After forming the abnormality suppression film on the silicon surface, the abnormality suppression film, for example, an abnormal growth suppression film is removed according to need, and then the process of patterning the silicon film and forming an insulating oxide film is performed.Type: ApplicationFiled: April 19, 2005Publication date: October 20, 2005Inventors: Toshihito Tsuga, Hirohiko Yamamoto, Michimasa Funabashi, Kazunori Nemoto
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Publication number: 20050067101Abstract: Semiconductor manufacturing apparatus and a manufacturing method of a semiconductor device capable of applying the single-wafer processing to the wet etching of a silicon nitride film are provided. Each one wafer is held by wafer holding means and etching solution is supplied to a deposited film of the wafer by etching solution supply means. The supplied etching solution is irradiated with electromagnetic wave by electromagnetic wave heating means so as to heat the etching solution to a high temperature and then the deposited film is wet-etched at a high etching rate. The wet etching with the process time appropriate for the single-wafer processing can be achieved. The used etching solution is collected by recycle means and is reused in the subsequent etching after adjusting its concentration.Type: ApplicationFiled: August 27, 2004Publication date: March 31, 2005Inventor: Michimasa Funabashi
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Publication number: 20040262265Abstract: A manufacturing method of semiconductor device capable of suppressing or preventing formation of a dissolution region of composition atoms such as a pit in a semiconductor wafer. After oxide film on a semiconductor wafer is removed by dipping plural pieces of the semiconductor wafer accommodated in a carrier into chemical liquid containing fluoro acid, chemical liquid adhering to the semiconductor wafer is washed out of the semiconductor wafer by rinse processing using de-ionized water. At least in the rinse processing of this wet processing, light is projected to the semiconductor wafer from a light source provided on a wet etching apparatus. Adjusting electromotive force caused by battery reaction at a pn junction of the semiconductor wafer by adjusting the state of the light L enables generation of a pit in the semiconductor wafer.Type: ApplicationFiled: June 25, 2004Publication date: December 30, 2004Applicant: Trecenti Technologies, Inc.Inventors: Michimasa Funabashi, Masakatsu Kuwabara, Kazunori Nemoto, Hiroyuki Mima, Norio Suzuki
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Patent number: 6794305Abstract: A processing solution containing hydrogen peroxide, hydracid fluoride salt, and water is used for pre-cleaning prior to a step of forming a gate oxide film 14 by subjecting a silicon wafer 1 to a heat treatment. Tetraalkyl ammonium fluoride, ammonium fluoride or the like is used as hydracid fluoride salt.Type: GrantFiled: July 12, 2001Date of Patent: September 21, 2004Assignee: Renesas Technology Corp.Inventor: Michimasa Funabashi
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Patent number: 6774047Abstract: A processing solution containing hydrogen peroxide, hydracid fluoride salt, and water is used for pre-cleaning prior to a step of forming a gate oxide film 14 by subjecting a silicon water 1 to a heat treatment. Tetraalkyl ammonium fluoride, ammonium fluoride or the like is used as hydracid fluoride salt.Type: GrantFiled: July 12, 2001Date of Patent: August 10, 2004Assignee: Renesas Technology Corp.Inventor: Michimasa Funabashi
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Patent number: 6727187Abstract: For providing a cleaning technique capable of removing metal contamination at a low temperature and in a short period of time, an aqueous solution containing 0.1 to 15% by weight of hydrochloric acid, 0.01 to 0.3% by weight of hydrofluoric acid and 0.1 to 15% by weight of hydrogen peroxide is used as a cleaning solution for cleaning a semiconductor substrate after forming a gate electrode of a polymetal structure on the semiconductor substrate.Type: GrantFiled: April 10, 2001Date of Patent: April 27, 2004Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Yutaka Takeshima, Michimasa Funabashi, Kenji Tanaka
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Publication number: 20040063263Abstract: A silicon oxide film is formed on the back side of a semiconductor substrate by using a CVD apparatus of a single wafer processing type, with a silicon oxide film deposited on the upper part of trenches on the semiconductor substrate placed downward, to form element isolation comprising the silicon oxide film, and then a MISFET is formed. As a result, even in a manufacturing process using mainly the single wafer processing, in which a film is not formed or hardly formed on the back side of the semiconductor substrate, deterioration of a gate insulating film due to charging-up of the semiconductor substrate, which occurs at the time of plasma processing, for example, at the time of forming a gate electrode or ashing of a resist film, can be prevented, and contamination of the back side of the semiconductor substrate can be prevented. Further, by performing lift-off cleaning which slightly etches the silicon oxide film, the cleaning efficiency can be improved.Type: ApplicationFiled: September 30, 2003Publication date: April 1, 2004Inventors: Norio Suzuki, Atsuyoshi Koike, Shinji Nishihara, Hirohiko Yamamoto, Kazunori Nemoto, Tadashi Suzuki, Michimasa Funabashi, Takeshi Kato
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Patent number: 6326255Abstract: A method for manufacturing a semiconductor device includes the steps of (1) forming a pad oxide film of 5 nm or more on a circuit forming surface of a semiconductor substrate; (2) forming an oxidation inhibition film on the pad oxide film; (3) forming grooves of a given depth with the oxidation inhibition film as a mask; (4) receding the pad oxide film; (5) oxidizing the grooves formed on the semiconductor substrate in the range of 0<C≦0.88t-924 in which the oxidizing atmosphere is dry oxidation (H2/O2≈0), the oxygen partial pressure in the air corresponding to the oxygen partial pressure ratio is C %, and the oxidizing temperature is t (° C.Type: GrantFiled: September 29, 2000Date of Patent: December 4, 2001Assignee: Hitachi, Ltd.Inventors: Norio Ishitsuka, Hideo Miura, Shuji Ikeda, Yasuko Yoshida, Norio Suzuki, Michimasa Funabashi
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Publication number: 20010039116Abstract: For providing a cleaning technique capable of removing metal contamination at a low temperature and in a short period of time, an aqueous solution containing 0.1 to 15% by weight of hydrochloric acid, 0.01 to 0.3% by weight of hydrofluoric acid and 0.1 to 15% by weight of hydrogen peroxide is used as a cleaning solution upon cleaning a semiconductor substrate after forming a gate electrode of a polymetal structure on the semiconductor substrate.Type: ApplicationFiled: April 10, 2001Publication date: November 8, 2001Inventors: Yutaka Takeshima, Michimasa Funabashi, Kenji Tanaka
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Publication number: 20010039122Abstract: A processing solution containing hydrogen peroxide, hydracid fluoride salt, and water is used for pre-cleaning prior to a step of forming a gate oxide film 14 by subjecting a silicon wafer 1 to a heat treatment. Tetraalkyl ammonium fluoride, ammonium fluoride or the like is used as hydracid fluoride salt.Type: ApplicationFiled: July 12, 2001Publication date: November 8, 2001Inventor: Michimasa Funabashi
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Publication number: 20010039123Abstract: A processing solution containing hydrogen peroxide, hydracid fluoride salt, and water is used for pre-cleaning prior to a step of forming a gate oxide film 14 by subjecting a silicon wafer 1 to a heat treatment. Tetraalkyl ammonium fluoride, ammonium fluoride or the like is used as hydracid fluoride salt.Type: ApplicationFiled: July 12, 2001Publication date: November 8, 2001Inventor: Michimasa Funabashi
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Patent number: 6284625Abstract: A method for manufacturing a semiconductor device includes the steps of (1) forming a pad oxide film of 5 nm or more on a circuit forming surface of a semiconductor substrate; (2) forming an oxidation inhibition film on the pad oxide film; (3) forming grooves of a given depth with the oxidation inhibition film as a mask; (4) receding the pad oxide film; (5) oxidizing the grooves formed on the semiconductor substrate in the range of 0<C≦0.88t−924 in which the oxidizing atmosphere is dry oxidation (H2/O2≈0), the oxygen partial pressure in the air corresponding to the oxygen partial pressure ratio is C %, and the oxidizing temperature is t (° C.Type: GrantFiled: November 5, 1999Date of Patent: September 4, 2001Assignee: Hitachi, Ltd.Inventors: Norio Ishitsuka, Hideo Miura, Shuji Ikeda, Yasuko Yoshida, Norio Suzuki, Michimasa Funabashi
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Patent number: 6277749Abstract: A processing solution containing hydrogen peroxide, hydracid fluoride salt, and water is used for pre-cleaning prior to a step of forming a gate oxide film 14 by subjecting a silicon wafer 1 to a heat treatment. Tetraalkyl ammonium fluoride, ammonium fluoride or the like is used as hydracid fluoride salt.Type: GrantFiled: September 9, 1999Date of Patent: August 21, 2001Assignee: Hiatchi, Ltd.Inventor: Michimasa Funabashi
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Patent number: 6029679Abstract: By employing a cleaning method wherein a substrate such as Si wafer is covered with a film having electrostatic repulsive force or a substance capable of controlling a zeta potential so as to prevent or remarkably reduce adhesion of fine particles present in a cleaning solution or etching solution, electronic parts can be produced in higher yield and lower cost.Type: GrantFiled: September 5, 1996Date of Patent: February 29, 2000Assignee: Hitachi, Ltd.Inventors: Katsuhiro Ota, Haruo Itoh, Akio Saito, Katsuhiko Itoh, Michimasa Funabashi
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Patent number: 5917211Abstract: A semiconductor integrated circuit comprising first n-channel MISFETs constituting the memory cells of a storage system, second n-channel MISFETs constituting the peripheral circuits of the storage system, and third n-channel MISFETs constituting the output circuit among the peripheral circuits. The respective threshold voltages of the first n-channel MISFETs, the second n-channel MISFETs and the third n-channel MISFETs are decreased in that order when the respective gate lengths of those MISFETs are substantially the same.Type: GrantFiled: November 25, 1997Date of Patent: June 29, 1999Assignee: Hitachi, Ltd.Inventors: Jun Murata, Yoshitaka Tadaki, Hiroko Kaneko, Toshihiro Sekiguchi, Hiroyuki Uchiyama, Hisashi Nakamura, Toshio Maeda, Osamu Kasahara, Hiromichi Enami, Atsushi Ogishima, Masaki Nagao, Michimasa Funabashi, Yasuo Kiguchi, Masayuki Kojima, Atsuyoshi Koike, Hiroyuki Miyazawa, Masato Sadaoka, Kazuya Kadota, Tadashi Chikahara, Kazuo Nojiri, Yutaka Kobayashi
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Patent number: 5734188Abstract: A semiconductor integrated circuit comprising first n-channel MISFETs constituting the memory cells of a storage system, second n-channel MISFETs constituting the peripheral circuits of the storage system, and third n-channel MISFETs constituting the output circuit among the peripheral circuits. The respective threshold voltages of the first n-channel MISFETs, the second n-channel MISFETs and the third n-channel MISFETs are decreased in that order when the respective gate lengths of those MISFETs are substantially the same.Type: GrantFiled: July 1, 1996Date of Patent: March 31, 1998Assignee: Hitachi, Ltd.Inventors: Jun Murata, Yoshitaka Tadaki, Hiroko Kaneko, Toshihiro Sekiguchi, Hiroyuki Uchiyama, Hisashi Nakamura, Toshio Maeda, Osamu Kasahara, Hiromichi Enami, Atsushi Ogishima, Masaki Nagao, Michimasa Funabashi, Yasuo Kiguchi, Masayuki Kojima, Atsuyoshi Koike, Hiroyuki Miyazawa, Masato Sadaoka, Kazuya Kadota, Tadashi Chikahara, Kazuo Nojiri, Yutaka Kobayashi
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Patent number: 5482524Abstract: An atmospheric pressure, elevated temperature gas desorption apparatus which enables quanitiative analysis of impurities absorbed in or on the surface of a solid sample (semiconductor wafer, optical disc, etc.) is disclosed. The atmospheric pressure, elevated temperature gas desorption apparatus for desorbing impurities absorbed in or on the surface of a plate-like solid sample 18 into a carrier gas 19 in a chamber 6 under an atmospheric pressure while increasing the temperature of the solid sample 18 includes a desorption room 7A provided in the chamber 6 and connected through to a first gas supply system 1 for supplying the carrier gas 19, for desorbing impurities absorbed in or on the surface of the solid sample 18 into the carrier gas 19. A sample support room 7B is provided in the chamber 6 and is separated from the desorption room 7A by a partition member 6A. The solid sample 18 is in close contact with the partition member 6A.Type: GrantFiled: August 3, 1994Date of Patent: January 9, 1996Assignees: Hitachi, Ltd., Hitachi Tokyo Electronics Co., Ltd.Inventors: Kazuo Nakano, Kazuaki Mizokami, Keiji Hasumi, Katsuhiko Itoh, Michimasa Funabashi, Yasuhiro Mitsui, Takashi Irie, Takeshi Tajima, Sadao Matsuoka