Abstract: A semiconductor device includes a first insulating film, a first wiring, a second insulating film, and a second wiring. The first insulating film is formed on a semiconductor substrate. The first wiring is formed on the first insulating film. The second insulating film is provided on the first insulating film to cover the first wiring. The second wiring is formed on the second insulating film. Furthermore, the second insulating film has a first opening part and a second opening part which expose the first wiring. The second wiring has a seed layer and a first plating layer. The first plating layer covers an entire side surface of the seed layer. The seed layer is not provided in the second opening part and a periphery thereof.

Abstract: A semiconductor device includes a first insulating film, a first wiring, a second insulating film, and a second wiring. The first insulating film is formed on a semiconductor substrate. The first wiring is formed on the first insulating film. The second insulating film is provided on the first insulating film to cover the first wiring. The second wiring is formed on the second insulating film. Furthermore, the second insulating film has a first opening part and a second opening part which expose the first wiring. The second wiring has a seed layer and a first plating layer. The first plating layer covers an entire side surface of the seed layer. The seed layer is not provided in the second opening part and a periphery thereof.

Abstract: In a wafer level CSP package, with respect to signal wiring 9b disposed in a signal wiring disposition forbidden region 16 in the vicinity of external output terminals disposed in a package outer peripheral portion, since a stress generated at signal wiring 9 can be dispersed by disposing dummy wiring 9a around the signal wiring 9b or by expanding the width of the signal wiring itself, occurrences of cracks in a surface protective film can be readily suppressed.

Abstract: A semiconductor device of the present invention includes: a wiring board 4 in which a conductive wiring 6 is formed on an insulating substrate 5 having an opening 5a; a semiconductor element 2 that has a circuit forming region 2a and an electrode pad 3, and is mounted on the wiring board with the circuit forming region facing the opening, the electrode pad being connected electrically to the conductive wiring via a protruding electrode 3a; a sealing resin 7 that covers the connected portion between the electrode pad and the conductive wiring; a heat dissipating member 9 that is disposed so as to have a portion facing the opening; and a filling material 8 that has a heat conductivity higher than that of the sealing resin, and is filled into the opening, so as to be in contact with the circuit forming region of the semiconductor element and the heat dissipating member. Even when the wiring board has a small area, heat dissipation efficiency can be ensured, and low cost manufacture can be achieved.

Abstract: An upper surface of a semiconductor substrate includes a first portion where a dielectric film is provided, and a second portion where the dielectric film is not provided, wherein the second portion is located in the periphery of the first portion. The upper surface of the semiconductor substrate is covered with a sealing resin.

Abstract: A semiconductor device includes an external terminal, a plurality of first interconnections, an electrode, a conductor, and a second interconnection. The first interconnections are positioned below the external terminal. The electrode is positioned at the same level as the first interconnections and is electrically connected to the external terminal through the conductor. The second interconnection is positioned below the first interconnections and the electrode. The semiconductor device has a region where the shortest distance between an edge surface of the electrode and an edge surface of one of the first interconnections positioned most adjacent to the electrode is less than 0.11 times the total thickness of the conductor and the electrode. The second interconnection is positioned at a position different from that of the region in a thickness direction of the semiconductor device.

Abstract: In a wafer level CSP package, with respect to signal wiring 9b disposed in a signal wiring disposition forbidden region 16 in the vicinity of external output terminals disposed in a package outer peripheral portion, since a stress generated at signal wiring 9 can be dispersed by disposing dummy wiring 9a around the signal wiring 9b or by expanding the width of the signal wiring itself, occurrences of cracks in a surface protective film can be readily suppressed.

Abstract: A flexible insulating base, a plurality of conductor wirings aligned on the flexible insulating base, and bump electrodes provided respectively in end portions of the plurality of conductor wirings in a region where a semiconductor chip is to be placed are provided. The semiconductor chip is mounted on the conductor wirings by bonding electrode pads formed on the semiconductor chip to the bump electrodes. An auxiliary conductor wiring formed similarly to the conductor wirings is provided on the insulating base, and an auxiliary bump electrode formed similarly to the bump electrodes is provided on the auxiliary conductor wiring, so that the electrode pads formed on the semiconductor chip can be registered with respect to the bump electrodes on the conductor wirings by positioning the semiconductor chip with reference to the auxiliary bump electrode.

Abstract: A semiconductor device of the present invention includes: a wiring board 4 in which a conductive wiring 6 is formed on an insulating substrate 5 having an opening 5a; a semiconductor element 2 that has a circuit forming region 2a and an electrode pad 3, and is mounted on the wiring board with the circuit forming region facing the opening, the electrode pad being connected electrically to the conductive wiring via a protruding electrode 3a; a sealing resin 7 that covers the connected portion between the electrode pad and the conductive wiring; a heat dissipating member 9 that is disposed so as to have a portion facing the opening; and a filling material 8 that has a heat conductivity higher than that of the sealing resin, and is filled into the opening, so as to be in contact with the circuit forming region of the semiconductor element and the heat dissipating member. Even when the wiring board has a small area, heat dissipation efficiency can be ensured, and low cost manufacture can be achieved.

Abstract: A wiring board includes: a flexible insulating base 1; a plurality of conductive wirings 2 arranged on the flexible insulating base 1; protruding electrodes 3 provided respectively at an end portion of the same side of each of the conductive wirings; external terminals 4, 5 formed respectively at the other end portions of each of the conductive wirings; metal plating layers applied on the conductive wirings, the protruding electrodes and the external terminals; and solder resist layers 7 formed respectively by coating the conductive wirings in regions between the end portions at which the protruding electrodes are provided and the external terminals. In the regions where the solder resist layers are formed, no metal plating layers are formed on the conductive wirings, and the surfaces of the conductive wirings to be contacted with the flexible insulating base are rougher than the surfaces not to be contacted with the flexible insulating base.

Abstract: A flexible insulating base, a plurality of conductor wirings aligned on the flexible insulating base, and bump electrodes provided respectively in end portions of the plurality of conductor wirings in a region where a semiconductor chip is to be placed are provided. The semiconductor chip is mounted on the conductor wirings by bonding electrode pads formed on the semiconductor chip to the bump electrodes. An auxiliary conductor wiring formed similarly to the conductor wirings is provided on the insulating base, and an auxiliary bump electrode formed similarly to the bump electrodes is provided on the auxiliary conductor wiring, so that the electrode pads formed on the semiconductor chip can be registered with respect to the bump electrodes on the conductor wirings by positioning the semiconductor chip with reference to the auxiliary bump electrode.

Abstract: A wiring board includes: a flexible insulating base 1; a plurality of conductive wirings 2 arranged on the flexible insulating base 1; protruding electrodes 3 provided respectively at an end portion of the same side of each of the conductive wirings; external terminals 4, 5 formed respectively at the other end portions of each of the conductive wirings; metal plating layers applied on the conductive wirings, the protruding electrodes and the external terminals; and solder resist layers 7 formed respectively by coating the conductive wirings in regions between the end portions at which the protruding electrodes are provided and the external terminals. In the regions where the solder resist layers are formed, no metal plating layers are formed on the conductive wirings, and the surfaces of the conductive wirings to be contacted with the flexible insulating base are rougher than the surfaces not to be contacted with the flexible insulating base.