Abstract: A repair circuit achieving “group repair of mixed multiple repair methods” and a repair design method for making a product margin suitable are provided. In a chip mounting multiple RAMs, a repair circuit and a repair design method in consideration of a trade-off of chip yield and area increase along with mounting a repair circuit are provided. A repair circuit achieving “group repair of mixed multiple repair methods” which can select existence of a repair circuit, and one or more repair methods from I/O, column, and row repairs on the RAMS in the chip, respectively, when a repair circuit is mounted. The repair circuit performs repair per RAM group by sorting the RAMs mounting a repair circuit into a plurality of RAM groups. Also, a repair method which makes a number of acquired good chips in a wafer and an estimation method of the RAM grouping method are provided.

Abstract: A fault test apparatus for testing a fault on each signal line in a circuit under test including signal lines includes a controller, which calculates a value of a fault excitation function for a fault signal line, using the fault excitation function representing a fitness result of a predetermined fault excitation condition between the fault signal line having a fault among the signal lines under test in the circuit under test and at least one of adjacent signal lines adjacent to the fault signal line and falling within a predetermined range from the fault signal line, based on layout information between the fault signal line and at least one adjacent signal line adjacent to the fault signal line, manufacturing parameter information, and timing information, and then, determines whether or not a dynamic fault is excited on the fault signal line based on the value of the fault excitation function.

Abstract: A semiconductor integrated circuit which can perform repair of at least one memory circuit in RAM, etc. and can promote improvement in the degree of integration is provided. The encoding circuit 3 receives the failure bit data fail [0]-fail [7], encodes these eight-bit failure bit data fail [7:0], and outputs four-bit (the number of compressed bits) encoded data ef [3:0] sequentially. This encoded data ef [3:0] can indicate various kinds of failure information about RAM1. The capture circuit 4 latches the encoded data ef [3:0] which satisfies a predetermined latch condition, as latch data cf [3:0]. The capture circuit 4 can perform a serial shift operation of the latch data cf [3:0], and can output serially the latch data cf [3:0] as the serial data output So.

Abstract: A repair circuit achieving “group repair of mixed multiple repair methods” and a repair design method for making a product margin suitable are provided. In a chip mounting multiple RAMs, a repair circuit and a repair design method in consideration of a trade-off of chip yield and area increase along with mounting a repair circuit are provided. A repair circuit achieving “group repair of mixed multiple repair methods” which can select existence of a repair circuit, and one or more repair methods from I/O, column, and row repairs on the RAMS in the chip, respectively, when a repair circuit is mounted. The repair circuit performs repair per RAM group by sorting the RAMs mounting a repair circuit into a plurality of RAM groups. Also, a repair method which makes a number of acquired good chips in a wafer and an estimation method of the RAM grouping method are provided.

Abstract: A semiconductor integrated circuit which can perform repair of at least one memory circuit in RAM, etc. and can promote improvement in the degree of integration is provided. The encoding circuit 3 receives the failure bit data fail [0]-fail [7], encodes these eight-bit failure bit data fail [7:0], and outputs four-bit (the number of compressed bits) encoded data ef [3:0] sequentially. This encoded data ef [3:0] can indicate various kinds of failure information about RAM1. The capture circuit 4 latches the encoded data ef [3:0] which satisfies a predetermined latch condition, as latch data cf [3:0]. The capture circuit 4 can perform a serial shift operation of the latch data cf [3:0], and can output serially the latch data cf [3:0] as the serial data output So.

Abstract: A fault test apparatus for testing a fault on each signal line in a circuit under test including signal lines includes a controller, which calculates a value of a fault excitation function for a fault signal line, using the fault excitation function representing a fitness result of a predetermined fault excitation condition between the fault signal line having a fault among the signal lines under test in the circuit under test and at least one of adjacent signal lines adjacent to the fault signal line and falling within a predetermined range from the fault signal line, based on layout information between the fault signal line and at least one adjacent signal line adjacent to the fault signal line, manufacturing parameter information, and timing information, and then, determines whether or not a dynamic fault is excited on the fault signal line based on the value of the fault excitation function.

Abstract: A semiconductor integrated circuit is provided whose area overhead due to provision of test points is reduced together with the test time period. In a semiconductor integrated circuit having a plurality of observation points in a tested circuit, the plurality of observation points are divided into a preset number of groups. The semiconductor integrated circuit contains at least one compressing circuit to reduce the number of bits of a multi-bit signal and to output the result (a signal of less bits) to an observable element such as an external output element or a flip-flop with a scan function. The semiconductor integrated circuit also has at least two scan chains each of which is made up with a plurality of flip-flop circuits working as shift registers. Further, the two scan chains are interconnected with a single input terminal.

Abstract: A semiconductor integrated circuit test method which reduces the required data volume for testing and efficiently detects faults in a circuit to be tested, the method comprising means 110 to generate identical pattern sequences repeatedly and means 120 to control flipped bits in pattern sequences, in order to generate neighborhood pattern sequences and use the neighborhood patterns to test the circuit under test 130. The neighborhood patterns include, in whole or in part, such pattern sequences as ones without flipped bits, ones with all or some flipped bits in one pattern and ones with all or some flipped bits in consecutive patterns or patterns at regular intervals, the interval being equivalent to a given number of patterns.

Abstract: A semiconductor integrated circuit is provided whose area overhead due to provision of test points is reduced together with the test time period. In a semiconductor integrated circuit having a plurality of observation points in a tested circuit, the plurality of observation points are divided into a preset number of groups. The semiconductor integrated circuit contains at least one compressing circuit to reduce the number of bits of a multi-bit signal and to output the result (a signal of less bits) to an observable element such as an external output element or a flip-flop with a scan function. The semiconductor integrated circuit also has at least two scan chains each of which is made up with a plurality of flip-flop circuits working as shift registers. Further, the two scan chains are interconnected with a single input terminal.

Abstract: An execution time of a built-in test utilizing a decoder can be shortened by setting in parallel the codes of test pattern generator during execution of a self-test in order to eliminate an event that a test execution time increases due to increase of the time required for setting the test codes when the number of test codes increases. Namely a semiconductor integrated circuit with a built-in test (BIT) function is provided with a test code backup register for storing the codes of a test pattern generator, a test clock generator and a BIT controller to realize a function to set the codes required for execution of the next self-test in parallel to execution of the self-test and a function to immediately shift to the next self-test upon completion of the first self-test execution. A tester periodically observes a self-test end signal BEND during execution of a self-test and immediately applies the next code to the semiconductor integrated circuit when it observes a signal indicating the end of the self-test.

Abstract: A method for designing a semiconductor integrated circuit while minimizing any increase in the area of its logic circuit under test. Circuit data about the semiconductor integrated circuit are received, and transition signal occurrence probabilities of all scanning function-equipped storage elements involved are computed by use of the circuit data. In keeping with the transition signal occurrence probabilities thus computed and based on predetermined parameters, the method permits selection of scanning function-equipped storage elements that may be replaced by delay test-ready scanning function-equipped storage elements.

Abstract: A semiconductor integrated circuit test method which reduces the required data volume for testing and efficiently detects faults in a circuit to be tested, the method comprising means 110 to generate identical pattern sequences repeatedly and means 120 to control flipped bits in pattern sequences, in order to generate neighborhood pattern sequences and use the neighborhood patterns to test the circuit under test 130. The neighborhood patterns include, in whole or in part, such pattern sequences as ones without flipped bits, ones with all or some flipped bits in one pattern and ones with all or some flipped bits in consecutive patterns or patterns at regular intervals, the interval being equivalent to a given number of patterns.

Abstract: A test point analyzing apparatus determines a distinction between capability and incapability of insertion of a test point and a circuit modifying way when a test point is capable of being inserted for each of the test point types to each of the signal lines in a semiconductor integrated circuit by using circuit information, a test point insertion library, and test point insertion. Then, test point indexes to test point candidates capable of being inserted are calculated, and test point candidates having a large testability are selected based on the indexes, and the selected test point candidates are registered in test point information. Such processing is repeated until a predetermined condition of completing the test point analysis process is realized.