Abstract: A semiconductor memory includes a memory transistor having a gate connected to a word line and having a threshold level selected from a plurality of threshold levels, and a plurality of comparison transistors having gates are respectively connected to the word line, each of the comparison transistor having a threshold level selected from the reference threshold levels and the threshold levels of the comparison transistor being different from each other. The word line is driven respectively to a plurality of voltage levels, and whenever they are driven to respective values of the plurality of voltage levels, the logical level state determined based on the difference between the current flowing in the memory transistor and the current flowing in the transistor circuit is held, and multibit data stored in the memory transistor is output based on the logical level state held.

Abstract: An asynchronous access type semiconductor memory device allows a memory cell array to supply a new data bit to an output data buffer unit for producing an output data signal indicative of the new data bit, and a data latching unit decides whether or not the new data bit is transferred to the output data buffer unit in view of lapse of time from address change to an address location assigned to a memory cell storing the new data bit so that the output data buffer unit is prevented from unexpected data bit read out upon false address change.