Abstract: A memory module having different types of memory mounted together on a double-sided substrate has a first edge and opposite second edge and includes a plurality of memory controllers, a plurality of flash memories, and a plurality of second memories having a higher signal transmission rate than the flash memories. A socket terminal for connecting the double-sided substrate to a motherboard is formed on the front surface and the back surface of the double-sided substrate on the first edge side; the memory controllers are disposed on the second edge side; the second memories are disposed on the second edge side at positions opposite the positions at which the memory controllers are disposed; and the flash memories are disposed on at least the back surface thereof at positions that are closer to the first edge than are the positions at which the memory controllers and the second memories are disposed.

Abstract: In methods connecting a memory module configured from DRAM, which is high-speed memory, and a memory module configured from flash memory which is slower than DRAM but is high-capacity memory, to a CPU memory bus, in the case of sequential reading, the busy rate of the CPU memory bus increases, and performance degradation occurs easily. In the present invention, an information processing device has a CPU, a CPU memory bus, and a primary storage device. The primary storage device has a first memory module and a second memory module. The first memory module has high-speed memory. The second memory module has memory having the same memory interface as that of the high-speed memory, high-capacity memory having a different memory interface from that of the high-speed memory, and a controller that controls same. The first memory module and second memory module are caused to be accessed by the memory interface of the high-speed memory.

Abstract: When DRAMs that are high-speed memories and flash memories that are lower in speed but can be larger in capacity than the DRAM are to be mounted on a DIMM, what matters in maximizing CPU memory bus throughput is the arrangement of the mounted components. The present disclosure provides a memory module (DIMM) that includes memory controllers arranged on the module surface closer to a socket terminal and DRAMs serving as high-speed memories arranged on the back surface. Nonvolatile memories as large-capacity memories are arranged on the side farther from the socket terminal.

Abstract: A memory module having different types of memory mounted together on a double-sided substrate has a first edge and opposite second edge and includes a plurality of memory controllers, a plurality of flash memories, and a plurality of second memories having a higher signal transmission rate than the flash memories. A socket terminal for connecting the double-sided substrate to a motherboard is formed on the front surface and the back surface of the double-sided substrate on the first edge side; the memory controllers are disposed on the second edge side; the second memories are disposed on the second edge side at positions opposite the positions at which the memory controllers are disposed; and the flash memories are disposed on at least the back surface thereof at positions that are closer to the first edge than are the positions at which the memory controllers and the second memories are disposed.

Abstract: When DRAMs that are high-speed memories and flash memories that are lower in speed but can be larger in capacity than the DRAM are to be mounted on a DIMM, what matters in maximizing CPU memory bus throughput is the arrangement of the mounted components. The present disclosure provides a memory module (DIMM) that includes memory controllers arranged on the module surface closer to a socket terminal and DRAMs serving as high-speed memories arranged on the back surface. Nonvolatile memories as large-capacity memories are arranged on the side farther from the socket terminal.

Abstract: In methods connecting a memory module configured from DRAM, which is high-speed memory, and a memory module configured from flash memory which is slower than DRAM but is high-capacity memory, to a CPU memory bus, in the case of sequential reading, the busy rate of the CPU memory bus increases, and performance degradation occurs easily. In the present invention, an information processing device has a CPU, a CPU memory bus, and a primary storage device. The primary storage device has a first memory module and a second memory module. The first memory module has high-speed memory. The second memory module has memory having the same memory interface as that of the high-speed memory, high-capacity memory having a different memory interface from that of the high-speed memory, and a controller that controls same. The first memory module and second memory module are caused to be accessed by the memory interface of the high-speed memory.

Abstract: By using switching power supplies a, b, and n, which have detection function of over-current, over-voltage and low voltage, in the case where a short-circuit occurred in a load which is connected to output of a switching power supply, and in the case where a MOSFET of the switching power supply is in a short-circuit state and broken, a main power is forced to be off, and a failure log of the switching power supply is stored in a non-volatile memory unit EEPROM; and also in the case where the main power was turned off and on, even if an abnormal log of the switching power supply logged in the non-volatile memory unit, reclosing of the main power is suppressed and which of the switching power supply occurred failure is notified to the outside.

Abstract: By using switching power supplies a, b, and n, which have detection function of over-current, over-voltage and low voltage, in the case where a short-circuit occurred in a load which is connected to output of a switching power supply, and in the case where a MOSFET of the switching power supply is in a short-circuit state and broken, a main power is forced to be off, and a failure log of the switching power supply is stored in a non-volatile memory unit EEPROM; and also in the case where the main power was turned off and on, even if an abnormal log of the switching power supply logged in the non-volatile memory unit, reclosing of the main power is suppressed and which of the switching power supply occurred failure is notified to the outside.

Abstract: An FM demodulator having a phase comparator, a low-pass filter and a VCO including a variable capacitance diode, an input signal being applied to the phase comparator and a demodulated output signal being taken from the low-pass filter. The FM demodulator further includes a compensating circuit consisting of a non-linear element connected between the demodulated output terminal and the VCO, whereby the secondary distortion in the output signal to be caused due to the non-linearity of the variable capacitance diode is canceled.

Abstract: There is disclosed a distortion cancel circuit in FM stereo receiver, which circuit synthesizes a canceling signal mainly including the distortion component by performing the arithmetic operation for an FM demodulation signal and adjusts the level of this synthesized canceling signal and thereafter subtractively combining it with the FM demodulation signal. This circuit enables the elimination of harmonic distortion which appears in the stereo MPX signal output due to the band characteristic of an intermediate frequency amplifier.

Abstract: There is provided an improvement of an FM demodulator of the PLL system including a VCO, a phase comparator and a low-pass filter, whereby the distortion components of the FM demodulated signal to be caused due to nonlinearity of the frequency vs. control voltage characteristic of the VCO are eliminated. This improved FM demodulator of the PLL system includes a circuit for making the harmonic distortion components from the output signal of the low-pass filter and synthesizing them with the output signal of the low-pass filter so as to obtain the non-distorted FM demodulated signal.

Abstract: In a distortion canceller to remove the distortion of a demodulated signal in an FM receiver, the n-th power of the demodulated FM signal is produced and then differentiated to derive an n-th order distortion signal. The derived n-th order distortion signal is adjusted in its amplitude level and then combined with the demodulated FM signal so that the n-th distortion component can be cancelled.

Abstract: A stereo multiplex circuit which can reduce a distortion of an FM demodulated signal to be generated due to nonlinearity of the frequency vs. amplitude/phase characteristics of a band-pass filter at an intermediate frequency amplifier stage of an FM receiver. This circuit includes a circuit for multiplying signals consisting of right-channel and left-channel signals and for adjusting the level of this multiplication signal into a suitable magnitude and thereafter inserting into the right and left channels, thereby causing a harmonic distortion to disappear.

Abstract: An FM stereo demodulator comprising a switching signal generator for providing four asymmetrical square wave switching signals whose phase differences from the subcarrier of the FM stereo composite signal are respectively 0.degree., 90.degree., 180.degree., and 270.degree. and whose frequencies are the same as the frequency of the subcarrier; four switching circuits for respectively switching the FM stereo composite signal using the four switching signals; and an undesired-beat cancellation circuit for producing left and right audio signals from the respective output signals of the four switching circuits by cancelling the undesired beat signals in the audio frequency zone, produced by the second harmonic component of the subcarrier and SCA signals contained in the FM stereo composite signals.

Abstract: A phase synchronizer for obtaining a signal which is phase synchronized with respect to another signal which has passed through a transmission system after originating at a signal source, the phase synchronizer comprising a variable phase shifter responsive to the output signal of the signal source for shifting the phase thereof in response to a control signal applied thereto; a phase comparator responsive to the signal which has passed through the transmission system and the output signal of the variable phase shifter to provide an output signal indicative of the phase difference between the two signals applied thereto; a low-pass filter responsive to the phase comparator output signal to provide the control signal for the variable phase shifter so that the phase of the output signal of the variable phase shifter follows the phase of the transmission system output signal.

Abstract: An oscillator suitable for use as a local oscillator of high frequency apparatus comprises a voltage controlled oscillator, a reference oscillator, a phase detector for detecting the phase difference between the oscillation frequencies of the voltage controlled oscillator and the reference oscillator, means for filtering the output of the phase detector to produce a DC voltage and a phase synchronizing loop for feeding back the DC output of the low-pass filter means to the voltage controlled oscillator. Depending upon whether the oscillation frequency of the reference oscillator is maintained at a duty cycle of 50% or at a value other than 50%, the oscillation frequency of the voltage controlled oscillator is synchronized with an odd multiple or an integer multiple of the oscillation frequency of the reference oscillator when the oscillation frequency of the voltage controlled oscillator is varied forcibly.