Michio Asano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
Abstract: In a netowrk system having a plurality of LANs each connecting a plurality of terminals interconnected, a LAN interconnection switching unit for switching and relaying data receives data frames from LANs and sends out a call set-up frame including a call number assigned to a combination of source and destination terminal addresses and addresses of relaying interconnection switching units. The data received from LAN is segmented into packets, which are sent out together with the call number. The interconnection switching unit switches and relays data by using data frame error detection scheme in the LAN. Information for controlling a switching sequence is added to the data frame from the LAN to prevent the interruption by the packet having a different call number.
Abstract: A laminated multilayer electric circuit is comprised of wafers having each internal electric circuits and laminated one after another. A signal transfer circuit used in the laminated multilayer electric circuit for transfer of signals between the wafers through an electrostatic capacitor has a receiving circuit of sufficiently high input resistance for receiving a signal from a capacitance electrode forming the electrostatic capacitor, and a circuit for clamping the level of the signal substantially within the input amplitude for the receiving circuit. The signal transfer circuit permits the signal transfer to be performed not through a flip-flop or the like and consequently at high speeds.
Abstract: An output circuit comprises an output transistor circuit for applying an output signal to a transmission line connected to an output terminal, a circuit for driving the output transistor circuit in response to an input signal applied to an input terminal, and a control circuit by which the signal amplitude of a first wave applicable to the transmission line with a load connected to the output terminal through the transmission line is rendered approximately one half of the output signal amplitude with a load directly connected to the output terminal. The control circuit includes a monitoring transistor within the same chip as the output transistor circuit, a selected one of the output resistance and input signal of the output transistor circuit being controlled in accordance with the magnitude of the drain current of the monitoring transistor to adjust the amplitude of the signal applied to the transmission line.
Abstract: An input buffer for a semiconductor circuit is provided with a source follower circuit composed of a first FET whose gate electrode has an input connected thereto, and a second FET of the same conductivity type as that of the first FET, whose drain electrode is connected to a source electrode of the first FET directly or through at least one level-shifting diode and whose gate electrode is supplied with a control voltage. The input buffer also includes a FET inverter circuit connected to the drain electrode of the second FET directly or through at least one level-shifting diode. An output signal for the input buffer is derived from the FET inverter circuit. A particular advantage of the present invention is that it permits the input buffer to switch its output from one level to another in response to input signals falling within a predetermined voltage range regardless of logic threshold level fluctuations in the FETs and fluctuations in supply voltages coupled to the input buffer.
Abstract: An input circuit is provided for converting an ECL level to a CMOS level. The input circuit of the invention includes a first input circuit having at least a P-type MOSFET and an N-type MOSFET connected in series. The gate of the P-type MOSFET is connected to the input of the circuit for receiving an input signal of the ECL level and the output of the circuit is taken out from between both MOSFETs. A voltage generation circuit is also provided for applying a voltage to the gate of the N-type MOSFET of the first input circuit to control the logic threshold voltage of the first input circuit. The voltage generation circuit includes a second circuit, which receives a logic threshold voltage of ECL as its input and is equivalent to the first input circuit, and an amplification circuit of at least one stage which receives the output of the second input circuit and the logic threshold voltage of CMOS as its input and amplifies the difference between them.
Abstract: A micro program control system for use in a data processing system includes a subsidiary control memory for storing the first micro instructions of respective micro programs, and a control memory for storing the second and the remaining micro instructions of the respective micro programs. The subsidinary control memory is coupled to a main memory in which macro instructions of a program for the data processing system are stored. The operation code of the macro instruction includes a code to address the first micro instruction in the subsidiary control memory, so that one of the first micro instructions can be accessed to supply into a control register when the macro instruction is read out from the main memory to an instruction register of the data processing system, whereby control signals for controlling the operation of the data processing system are delivered from the control register according to the contents of the first micro instruction.