Abstract: In the shipment test of an LSI provided with a high-speed interface circuit, both cost reduction and a high test guarantee level are realized.

Abstract: A plurality of testing units, each of which is applied to an input or output terminal of a device under test, are provided. An input pattern is supplied to a first testing unit that is applied to an input terminal, while expected patterns are supplied to second and third testing units that are applied to first and second output terminals, respectively. These testing units are operated in synchronism with a common clock signal. The second testing unit, which has received the expected pattern, communicates an evaluative result, indicating a point in time when the logical level of a voltage signal appearing at the first output terminal of the device under test matches with the expected pattern, to the third testing unit. And the third testing unit performs timing and functional tests on a signal appearing at the second output terminal with reference to this evaluative result.

Abstract: The invention relates to a method for reducing the time required to test the functions of a semiconductor device. Test modules, each having a plurality of test statements, are created for testing predetermined functions of the device. Common test statements are extracted from the test modules. A test program is then produced by sequentially arranging the extracted statement(s) and the remaining statements from the test modules.