Patents by Inventor Michio Morita

Michio Morita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150203734
    Abstract: A heat storage material composition comprising: (A) a linear saturated hydrocarbon compound having 2n carbon atoms; (B) a linear saturated hydrocarbon compound having (2n+m) carbon atoms; and (C) an organic compound having a molecular weight of 50 to 300, a solubility parameter of 5 to 8.5 (cal/cm3)0.5 and a melting point measured by a differential scanning calorimeter which is 30° C.
    Type: Application
    Filed: August 9, 2013
    Publication date: July 23, 2015
    Applicant: JSR CORPORATION
    Inventors: Kentarou Kanae, Susumu Komiyama, Michio Morita
  • Patent number: 6967165
    Abstract: A method for forming a multilayer interconnect includes: a first step of forming a lower layer interconnect in an upper portion of a first insulating film and then forming a second insulating film and a third insulating film in this order on the first insulating film including the lower layer interconnect; a second step of forming an aperture in part of the third insulating film located above the lower layer interconnect; a third step of forming an interconnect groove in an upper portion of the third insulating film so that an upper portion of the aperture is part of the interconnect groove while reducing the thickness of part of the second insulating film located under the aperture without having the lower layer interconnect exposed; a fourth step of removing part of the second insulating film located under the aperture to expose the lower layer interconnect; and a fifth step of filling a conductive film in the aperture and the interconnect groove and thereby forming an upper layer interconnect and a connect
    Type: Grant
    Filed: July 29, 2003
    Date of Patent: November 22, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Michio Morita
  • Publication number: 20040115915
    Abstract: A method for forming a multilayer interconnect includes: a first step of forming a lower layer interconnect in an upper portion of a first insulating film and then forming a second insulating film and a third insulating film in this order on the first insulating film including the lower layer interconnect; a second step of forming an aperture in part of the third insulating film located above the lower layer interconnect; a third step of forming an interconnect groove in an upper portion of the third insulating film so that an upper portion of the aperture is part of the interconnect groove while reducing the thickness of part of the second insulating film located under the aperture without having the lower layer interconnect exposed; a fourth step of removing part of the second insulating film located under the aperture to expose the lower layer interconnect; and a fifth step of filling a conductive film in the aperture and the interconnect groove and thereby forming an upper layer interconnect and a connect
    Type: Application
    Filed: July 29, 2003
    Publication date: June 17, 2004
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD
    Inventor: Michio Morita
  • Patent number: 6143609
    Abstract: A floating gate type semiconductor memory and method of manufacture are described including an erasing gate electrode in which a tunneling region can be formed easily and high reliability can be kept. An active region isolated by element isolation insulating films is formed on a semiconductor substrate. A gate insulating film and a floating gate electrode are sequentially formed on the active region. A control gate electrode is formed above the floating gate electrode with a silicon oxide film disposed therebetween. A tunneling insulating film is formed only on the side wall of the floating gate electrode. Then, an erasing gate electrode is formed so as to cover the tunneling insulating film.
    Type: Grant
    Filed: December 2, 1996
    Date of Patent: November 7, 2000
    Assignee: Matsushita Electronics Corporation
    Inventors: Kazuo Sato, Kenji Ueda, Michio Morita, Fumihiko Noro, Kyoko Miyamoto, Hideaki Onishi, Kazuo Umeda, Kazuya Kubo
  • Patent number: 5838039
    Abstract: A floating gate type semiconductor memory and method of manufacture are described including an erasing gate electrode in which a tunneling region can be formed easily and high reliability can be kept. An active region isolated by element isolation insulating films is formed on a semiconductor substrate. A gate insulating film and a floating gate electrode are sequentially formed on the active region. A control gate electrode is formed above the floating gate electrode with a silicon oxide film disposed therebetween. A tunneling insulating firm is formed only on the side wall of the floating gate electrode. Then, an erasing gate electrode is formed so as to cover the tunneling insulating film.
    Type: Grant
    Filed: July 8, 1996
    Date of Patent: November 17, 1998
    Assignee: Matsushita Electronics Corporation
    Inventors: Kazuo Sato, Kenji Ueda, Michio Morita, Fumihiko Noro, Kyoko Miyamoto, Hideaki Onishi, Kazuo Umeda, Kazuya Kubo
  • Patent number: 4992374
    Abstract: An improved mutant vaccinia virus providing a pock and plaque size on RK13 cells that is approximately the same as those of the Lister original, having a proliferation potency on YTV cells that is approximately the same as that of the Lister original, and having a neurovirulence, assessed by a recovery of an intrabrain virus, that is lower than that of the Lister original; and a process for the production thereof.
    Type: Grant
    Filed: July 30, 1987
    Date of Patent: February 12, 1991
    Assignees: Toa Nenryo Kogyo Kabushiki Kaisha, Chiba Prefecture
    Inventors: Masanobu Sugimoto, Fukumi Nishimaki, Tadashi Maruyama, Keizaburo Miki, Michio Morita, Kazuyoshi Suzuki
  • Patent number: 4567147
    Abstract: The present invention discloses an attenuated smallpox vaccine strain exhibiting antibody production similar to conventional strains but without postvaccinal side effects. The vaccine is prepared by attenuating a Lister strain of a vaccinia virus by cell culture and selecting a suitable strain therefrom showing relatively small and uniform pocks on the chorioallantoic membrane of an embryonated egg.
    Type: Grant
    Filed: December 20, 1984
    Date of Patent: January 28, 1986
    Assignee: Chiba Prefectural Government
    Inventors: Kiyoshi Ooi, Michio Morita, Kazuyoshi Suzuki, Soh Hashizume, Hanako Yoshizawa