Abstract: Provided is a pattern inspection device for accurately simulating an electron beam image of a circuit pattern on a wafer from design data, and implementing high-precision defect detection based on the comparison between the simulated electron beam image and a real image. A pattern inspection device comprises: an image capturing unit for capturing an electron beam image of a pattern formed on a substrate; a simulated electron beam image generation unit for generating a simulated electron beam image using a parameter indicating the characteristics of the electron beam image on the basis of design data; and an inspection unit for comparing the electron beam image of the pattern, which is the image captured by the image capturing unit, and the simulated electron beam image generated by the simulated electron beam image generation unit, and inspecting the pattern on the substrate.

Abstract: Provided is a pattern inspection device for accurately simulating an electron beam image of a circuit pattern on a wafer from design data, and implementing high-precision defect detection based on the comparison between the simulated electron beam image and a real image. A pattern inspection device comprises: an image capturing unit for capturing an electron beam image of a pattern formed on a substrate; a simulated electron beam image generation unit for generating a simulated electron beam image using a parameter indicating the characteristics of the electron beam image on the basis of design data; and an inspection unit for comparing the electron beam image of the pattern, which is the image captured by the image capturing unit, and the simulated electron beam image generated by the simulated electron beam image generation unit, and inspecting the pattern on the substrate.

Abstract: A pattern inspection apparatus has a setting unit of a plurality of cell areas A and B of different cell comparison pitches and inspects the plurality of cell areas of the different cell comparison pitches in accordance with settings of the setting unit. As information to read out image data for an inspection image and a reference image from an image memory, in addition to position information of a defective image, identification information showing either a cell comparison or a die comparison and relative position information of the reference image can be set. The apparatus also has a unit for setting a plurality of inspection threshold values every inspection area and inspects a plurality of inspection areas by the plurality of inspection threshold values.

Abstract: An image processing apparatus for wafer inspection tool that is able to perform continuously cell to cell comparison inspection, die to die comparison inspection, and cell-to-cell and die-to-die hybrid comparison inspection, employing a plurality of processors. This image processing apparatus for wafer inspection tool comprises a plurality of processors for performing parallel processing, means for cutting out image data including a forward end overlap and a rear end overlap at partition boundaries in order to cut serial data into a predetermined image size, means for distributing the cutout image data to the plurality of processors, and means for assembling results of processing performed by the plurality of processors. The forward end overlap is set greater than a pitch of the cell subject to cell to cell comparison inspection.

Abstract: A pattern inspection apparatus has a setting unit of a plurality of cell areas A and B of different cell comparison pitches and inspects the plurality of cell areas of the different cell comparison pitches in accordance with settings of the setting unit. As information to read out image data for an inspection image and a reference image from an image memory, in addition to position information of a defective image, identification information showing either a cell comparison or a die comparison and relative position information of the reference image can be set. The apparatus also has a unit for setting a plurality of inspection threshold values every inspection area and inspects a plurality of inspection areas by the plurality of inspection threshold values.

Abstract: An image processing apparatus for wafer inspection tool that is able to perform continuously cell to cell comparison inspection, die to die comparison inspection, and cell-to-cell and die-to-die hybrid comparison inspection, employing a plurality of processors. This image processing apparatus for wafer inspection tool comprises a plurality of processors for performing parallel processing, means for cutting out image data including a forward end overlap and a rear end overlap at partition boundaries in order to cut serial data into a predetermined image size, means for distributing the cutout image data to the plurality of processors, and means for assembling results of processing performed by the plurality of processors. The forward end overlap is set greater than a pitch of the cell subject to cell to cell comparison inspection.

Abstract: An image processing apparatus for wafer inspection tool that is able to perform continuously cell to cell comparison inspection, die to die comparison inspection, and cell-to-cell and die-to-die hybrid comparison inspection, employing a plurality of processors. This image processing apparatus for wafer inspection tool comprises a plurality of processors for performing parallel processing, means for cutting out image data including a forward end overlap and a rear end overlap at partition boundaries in order to cut serial data into a predetermined image size, means for distributing the cutout image data to the plurality of processors, and means for assembling results of processing performed by the plurality of processors. The forward end overlap is set greater than a pitch of the cell subject to cell to cell comparison inspection.

Abstract: An inspection apparatus includes an irradiation optical system for irradiating an inspection target with an electron beam, a scanning unit for scanning an irradiation position in the X direction and the Y direction, an electrification control electrode for controlling secondary electrons or reflected electrons generated on the inspection target by the irradiation with the electron beam, a sensor for detecting the secondary electrons or the reflected electrons, an A/D converter for sequentially converting the signals into digital image signals from an irradiation start point-in-time of the electron beam, an addition circuit for creating a detection image by adding the digital image signals from a first set point-in-time to a second set point-in-time on each pixel basis, and an image processing circuit for judging a defect by comparing the detection image with a reference image of a circuit pattern formed on the inspection target.

Abstract: A pattern inspection apparatus has a setting unit of a plurality of cell areas A and B of different cell comparison pitches and inspects the plurality of cell areas of the different cell comparison pitches in accordance with settings of the setting unit. As information to read out image data for an inspection image and a reference image from an image memory, in addition to position information of a defective image, identification information showing either a cell comparison or a die comparison and relative position information of the reference image can be set. The apparatus also has a unit for setting a plurality of inspection threshold values every inspection area and inspects a plurality of inspection areas by the plurality of inspection threshold values.

Abstract: An image processing apparatus for wafer inspection tool that is able to perform continuously cell to cell comparison inspection, die to die comparison inspection, and cell-to-cell and die-to-die hybrid comparison inspection, employing a plurality of processors. This image processing apparatus for wafer inspection tool comprises a plurality of processors for performing parallel processing, means for cutting out image data including a forward end overlap and a rear end overlap at partition boundaries in order to cut serial data into a predetermined image size, means for distributing the cutout image data to the plurality of processors, and means for assembling results of processing performed by the plurality of processors. The forward end overlap is set greater than a pitch of the cell subject to cell to cell comparison inspection.

Abstract: Thin-walled molded articles (i.e., molded articles where at least 70% of the wall thickness is 0.8 mm or less) are formed of a polybutylene terephthalate (PBT) molding composition having improved fluidity characteristics and desirable mechanical strength properties. The PBT molding composition includes (A) 100 parts by weight of a polybutylene terephthalate base resin having a melt index of between 40 and 200 as measured at 235.degree. C. under a load of 2160 grams according to ASTM D-1238; (B) between 1 to 60 parts by weight of plate-like glass flakes having an average flake dimension of between 10 to 200 .mu.m; and (C) between 0.01 to 5 parts by weight of a fatty acid metal salt.

Abstract: A resin composition comprises a polybutylene terephthalate, a halogenated bisimide having the formula (1) and a polytetrafluoroethylene resin and is improved in flame retardancy and at the same time moulding properties. It is useful for parts of electric instruments.