Abstract: A thin film transistor in which a device active layer is formed on an insulation film, in which an interface state density present at the interface between the active layer and the insulation film is set to less than 1.times.10.sup.11 /cm.sup.2. The characteristics of TFT can be enhanced by decreasing the leak current and SRAM memory cell can be provided with easy design for the process and the structure while avoiding increase in the resistance and additional capacitance and ensuring voltage withstand.

Abstract: A thin film transistor in which a device active layer is formed on an insulation film, in which an interface state density present at the interface between the active layer and the insulation film is set to less than 1.times.10.sup.11 /cm.sup.2. The characteristics of TFT can be enhanced by decreasing the leak current and SRAM memory cell can be provided with easy design for the process and the structure while avoiding increase in the resistance and additional capacitance and ensuring voltage withstand.

Abstract: A thin film transistor in which a device active layer is formed on an insulation film. In which an interface state density present at the interface between the active layer and the insulation film is set to less than 1.times.10.sup.11 /cm.sup.2. The characteristics of TFT can be enhanced by decreasing the leak current and SRAM memory cell can be provided with easy design for the process and the structure while avoiding increase in the resistance and additional capacitance and ensuring voltage withstand.

Abstract: An exposure mask and an exposure method are provided, which can suppress adverse effects of interference edge patterns (sub-shifters) located around a central pattern.The exposure mask has central patterns and edge patterns arranged around each central pattern. The mutual interference of edge patterns is reduced by providing an angle or a phase difference between vicinity edge patterns, or providing a single edge pattern to reduce the light transmission.

Abstract: An SRAM memory cell structure, wherein a word line is disposed near the center of a cell, each one of driver transistors is disposed on both sides thereof substantially in parallel with each other, a contact portion for a gate electrode of said driver transistor is formed being laminated on a word transistor formed together with said word line, and a semiconductor, wherein an upper transistor and a lower transistor are disposed, an overlapped portion in which at least three layers each having a diffusion region for forming each of said transistors are overlapped is formed, and a contact is taken at said overlapped portion.

Abstract: A CCD imager wherein signal charge can be transferred at a high speed and smears can be minimized without employing a complicated wiring configuration. The CCD imager comprises a transfer electrode formed from a semiconductor layer, a light intercepting film formed from a first layer metal film on the transfer electrode, and a shunt wiring film formed from a second layer metal film on the first layer metal film. The transfer electrode and the shunt wiring film are electrically connected to each other by way of the light intercepting film. Also an improved CCD imager of the frame interline type is disclosed wherein a storage section is improved in light intercepting performance to prevent possible occurrence of smears at the storage section with a simplified configuration of wiring in the storage section.

Abstract: A thin film MOS transistor has a construction which can minimize scattering of electron and thus maximize electrons mobility for allowing higher speed operation of the transistor. For this, the MOS transistor has a thin film semiconductor layer having a thickness in a range less than or equal to 100 nm, between a pair of gate electrodes which oppose each other across the semiconductor layer.