Patents by Inventor Michio Nemoto
Michio Nemoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10043865Abstract: A p anode layer is formed on one main surface of an n? drift layer. N+ cathode layer having an impurity concentration more than that of the n? drift layer is formed on the other main surface. An anode electrode is formed on the surface of the p anode layer. A cathode electrode is formed on the surface of the n+ cathode layer. N-type broad buffer region having a net doping concentration more than the bulk impurity concentration of a wafer and less than the n+ cathode layer and p anode layer is formed in the n? drift layer. Resistivity ?0 of the n? drift layer satisfies 0.12V0??0?0.25V0 with respect to rated voltage V0. Total amount of net doping concentration of the broad buffer region is equal to or more than 4.8×1011 atoms/cm2 and equal to or less than 1.0×1012 atoms/cm2.Type: GrantFiled: December 28, 2015Date of Patent: August 7, 2018Assignee: FUJI ELECTRIC CO., LTD.Inventors: Michio Nemoto, Takashi Yoshimura
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Publication number: 20160111489Abstract: A p anode layer is formed on one main surface of an n? drift layer. N+ cathode layer having an impurity concentration more than that of the n? drift layer is formed on the other main surface. An anode electrode is formed on the surface of the p anode layer. A cathode electrode is formed on the surface of the n+ cathode layer. N-type broad buffer region having a net doping concentration more than the bulk impurity concentration of a wafer and less than the n+ cathode layer and p anode layer is formed in the n? drift layer. Resistivity ?0 of the n? drift layer satisfies 0.12V0??0?0.25V0 with respect to rated voltage V0. Total amount of net doping concentration of the broad buffer region is equal to or more than 4.8×1011 atoms/cm2 and equal to or less than 1.0×1012 atoms/cm2.Type: ApplicationFiled: December 28, 2015Publication date: April 21, 2016Inventors: Michio NEMOTO, Takashi YOSHIMURA
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Patent number: 9252209Abstract: A p anode layer is formed on one main surface of an n? drift layer. N+ cathode layer having an impurity concentration more than that of the n? drift layer is formed on the other main surface. An anode electrode is formed on the surface of the p anode layer. A cathode electrode is formed on the surface of the n+ cathode layer. N-type broad buffer region having a net doping concentration more than the bulk impurity concentration of a wafer and less than the n+ cathode layer and p anode layer is formed in the n? drift layer. Resistivity ?0 of the n? drift layer satisfies 0.12V0??0?0.25V0 with respect to rated voltage V0. Total amount of net doping concentration of the broad buffer region is equal to or more than 4.8×1011 atoms/cm2 and equal to or less than 1.0×1012 atoms/cm2.Type: GrantFiled: June 4, 2015Date of Patent: February 2, 2016Assignee: FUJI ELECTRIC CO., LTD.Inventors: Michio Nemoto, Takashi Yoshimura
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Publication number: 20150303248Abstract: A p anode layer is formed on one main surface of an n? drift layer. N+ cathode layer having an impurity concentration more than that of the n? drift layer is formed on the other main surface. An anode electrode is formed on the surface of the p anode layer. A cathode electrode is formed on the surface of the n+ cathode layer. N-type broad buffer region having a net doping concentration more than the bulk impurity concentration of a wafer and less than the n+ cathode layer and p anode layer is formed in the n? drift layer. Resistivity ?0 of the n? drift layer satisfies 0.12V0??0?0.25V0 with respect to rated voltage V0. Total amount of net doping concentration of the broad buffer region is equal to or more than 4.8×1011 atoms/cm2 and equal to or less than 1.0×1012 atoms/cm2.Type: ApplicationFiled: June 4, 2015Publication date: October 22, 2015Inventors: Michio NEMOTO, Takashi YOSHIMURA
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Patent number: 9070658Abstract: A p anode layer (2) is formed on one main surface of an n? drift layer (1). An n+ cathode layer (3) having an impurity concentration more than that of the n? drift layer (1) is formed on the other main surface of the n? drift layer (1). An anode electrode (4) is formed on the surface of the p anode layer (2). A cathode electrode (5) is formed on the surface of the n+ cathode layer (3). An n-type broad buffer region (6) that has a net doping concentration more than the bulk impurity concentration of a wafer and less than that of the n+ cathode layer (3) and the p anode layer (2) is formed in the n? drift layer (1). The resistivity ?0 of the n? drift layer (1) satisfies 0.12V0??0?0.25V0 with respect to a rated voltage V0. The total amount of the net doping concentration of the broad buffer region (6) is equal to or more than 4.8×1011 atoms/cm2 and equal to or less than 1.0×1012 atoms/cm2.Type: GrantFiled: May 21, 2014Date of Patent: June 30, 2015Assignee: FUJI ELECTRIC CO., LTD.Inventors: Michio Nemoto, Takashi Yoshimura
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Patent number: 8957461Abstract: A TMBS diode is disclosed. In an active portion and voltage withstanding structure portion of the diode, an end portion trench surrounds active portion trenches. An active end portion which is an outer circumferential side end portion of an anode electrode is in contact with conductive polysilicon inside the end portion trench. A guard trench is separated from the end portion trench and surrounds it. A field plate provided on an outer circumferential portion of the anode electrode is separated from the anode electrode, and contacts both part of a surface of n-type drift layer in a mesa region between the end portion trench and the guard trench and the conductive polysilicon formed inside the guard trench. The semiconductor device has high withstand voltage without injection of minority carriers, and relaxed electric field intensity of the trench formed in an end portion of an active portion.Type: GrantFiled: July 29, 2013Date of Patent: February 17, 2015Assignee: Fuji Electric Co., Ltd.Inventors: Tomonori Mizushima, Michio Nemoto
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Publication number: 20140284657Abstract: A p anode layer (2) is formed on one main surface of an n? drift layer (1). An n+ cathode layer (3) having an impurity concentration more than that of the n? drift layer (1) is formed on the other main surface of the n? drift layer (1). An anode electrode (4) is formed on the surface of the p anode layer (2). A cathode electrode (5) is formed on the surface of the n+ cathode layer (3). An n-type broad buffer region (6) that has a net doping concentration more than the bulk impurity concentration of a wafer and less than that of the n+ cathode layer (3) and the p anode layer (2) is formed in the n? drift layer (1). The resistivity ?0 of the n? drift layer (1) satisfies 0.12V0??0?0.25V0 with respect to a rated voltage V0. The total amount of the net doping concentration of the broad buffer region (6) is equal to or more than 4.8×1011 atoms/cm2 and equal to or less than 1.0×1012 atoms/cm2.Type: ApplicationFiled: May 21, 2014Publication date: September 25, 2014Applicant: FUJI ELECTRIC CO., LTD.Inventors: Michio NEMOTO, Takashi YOSHIMURA
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Patent number: 8766413Abstract: A p anode layer (2) is formed on one main surface of an n? drift layer (1). An n+ cathode layer (3) having an impurity concentration more than that of the n? drift layer (1) is formed on the other main surface of the n? drift layer (1). An anode electrode (4) is formed on the surface of the p anode layer (2). A cathode electrode (5) is formed on the surface of the n+ cathode layer (3). An n-type broad buffer region (6) that has a net doping concentration more than the bulk impurity concentration of a wafer and less than that of the n+ cathode layer (3) and the p anode layer (2) is formed in the n? drift layer (1). The resistivity ?0 of the n? drift layer (1) satisfies 0.12V0??0?0.25V0 with respect to a rated voltage V0. The total amount of the net doping concentration of the broad buffer region (6) is equal to or more than 4.8×1011 atoms/cm2 and equal to or less than 1.0×1012 atoms/cm2.Type: GrantFiled: November 2, 2010Date of Patent: July 1, 2014Assignee: Fuji Electric Co., Ltd.Inventors: Michio Nemoto, Takashi Yoshimura
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Patent number: 8716826Abstract: In a semiconductor device having a pn-junction diode structure that includes anode diffusion region including edge area, anode electrode on anode diffusion region, and insulator film on edge area of anode diffusion region, the area of anode electrode above anode diffusion region with insulator film interposed between anode electrode and anode diffusion region is narrower than the area of insulator film on edge area of anode diffusion region.Type: GrantFiled: April 16, 2012Date of Patent: May 6, 2014Assignee: Fuji Electric Co., Ltd.Inventors: Ryouichi Kawano, Tomoyuki Yamazaki, Michio Nemoto, Mituhiro Kakefu
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Publication number: 20130307111Abstract: A TMBS diode is disclosed. In an active portion and voltage withstanding structure portion of the diode, an end portion trench surrounds active portion trenches. An active end portion which is an outer circumferential side end portion of an anode electrode is in contact with conductive polysilicon inside the end portion trench. A guard trench is separated from the end portion trench and surrounds it. A field plate provided on an outer circumferential portion of the anode electrode is separated from the anode electrode, and contacts both part of a surface of n-type drift layer in a mesa region between the end portion trench and the guard trench and the conductive polysilicon formed inside the guard trench. The semiconductor device has high withstand voltage without injection of minority carriers, and relaxed electric field intensity of the trench formed in an end portion of an active portion.Type: ApplicationFiled: July 29, 2013Publication date: November 21, 2013Applicant: Fuji Electric Co., Ltd.Inventors: Tomonori MIZUSHIMA, Michio NEMOTO
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Patent number: 8502345Abstract: Reverse-conducting insulated gate bipolar transistor in which IGBT region and FWD region are integrated into a single body in a semiconductor substrate with a common active region is disclosed. MOS gate structure is on a first major surface side. Rear surface side structure is in a second major surface side of the semiconductor substrate and includes a plurality of recessed parts vertical to the second major surface, which are repeated periodically along the second major surface. A plurality of protruding parts are interposed between the recessed parts. Rear surface side structure includes p type collector region on a bottom surface of the recessed part, n type first field stop region at a position deeper than the collector region, n type cathode region on the top surface of the protruding part, and n type second field stop region in the protruding part at a position deeper than the cathode region.Type: GrantFiled: January 27, 2011Date of Patent: August 6, 2013Assignee: Fuji Electric Co., Ltd.Inventors: Michio Nemoto, Souichi Yoshida
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Publication number: 20120267681Abstract: A p anode layer (2) is formed on one main surface of an n? drift layer (1). An n+ cathode layer (3) having an impurity concentration more than that of the n? drift layer (1) is formed on the other main surface of the n? drift layer (1). An anode electrode (4) is formed on the surface of the p anode layer (2). A cathode electrode (5) is formed on the surface of the n+ cathode layer (3). An n-type broad buffer region (6) that has a net doping concentration more than the bulk impurity concentration of a wafer and less than that of the n+ cathode layer (3) and the p anode layer (2) is formed in the n? drift layer (1). The resistivity ?0 of the n? drift layer (1) satisfies 0.12V0??0?0.25V0 with respect to a rated voltage V0. The total amount of the net doping concentration of the broad buffer region (6) is equal to or more than 4.8×1011 atoms/cm2 and equal to or less than 1.0×1012 atoms/cm2.Type: ApplicationFiled: November 2, 2010Publication date: October 25, 2012Applicant: FUJI ELECTRIC CO., LTD.Inventors: Michio Nemoto, Takashi Yoshimura
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Publication number: 20120193749Abstract: In a semiconductor device having a pn-junction diode structure that includes anode diffusion region including edge area, anode electrode on anode diffusion region, and insulator film on edge area of anode diffusion region, the area of anode electrode above anode diffusion region with insulator film interposed between anode electrode and anode diffusion region is narrower than the area of insulator film on edge area of anode diffusion region.Type: ApplicationFiled: April 16, 2012Publication date: August 2, 2012Applicant: Fuji Electric Device Technology Co., Ltd.Inventors: Ryouichi KAWANO, Tomoyuki Yamazaki, Michio Nemoto, Mituhiro Kakefu
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Patent number: 8178941Abstract: In a semiconductor device having a pn-junction diode structure that includes anode diffusion region including edge area, anode electrode on anode diffusion region, and insulator film on edge area of anode diffusion region, the area of anode electrode above anode diffusion region with insulator film interposed between anode electrode and anode diffusion region is narrower than the area of insulator film on edge area of anode diffusion region.Type: GrantFiled: July 22, 2009Date of Patent: May 15, 2012Assignee: Fuji Electric Co., Ltd.Inventors: Ryouichi Kawano, Tomoyuki Yamazaki, Michio Nemoto, Mituhiro Kakefu
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Patent number: 8163630Abstract: A method of manufacturing a semiconductor device by thinning a substrate by grinding, and performing ion implantation. In a diode in which a P anode layer and an anode electrode are formed at a side of a right face of an N? drift layer, and an N+ cathode layer and a cathode electrode are formed at a side of a back face of the N? drift layer, an N cathode buffer layer is formed thick compared with the N+-type cathode layer between the N?-type drift layer and the N+ cathode layer, the buffer layer being high in concentration compared with the N? drift layer, and low compared with the N+ cathode layer. When a reverse bias voltage is applied, a depletion layer is stopped in the middle of the N cathode buffer layer, and thus prevented from reaching the N+ cathode layer, so that the leakage current is suppressed.Type: GrantFiled: April 13, 2010Date of Patent: April 24, 2012Assignee: Fuji Electric Co., Ltd.Inventor: Michio Nemoto
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Publication number: 20120064706Abstract: A semiconductor device is provided in which a semiconductor substrate can be prevented from being broken while elements can be prevented from being destroyed by a snap-back phenomenon. After an MOS gate structure is formed in a front surface of an FZ wafer, a rear surface of the FZ wafer is ground. Then, the ground surface is irradiated with protons and irradiated with two kinds of laser beams different in wavelength simultaneously to thereby form an N+ first buffer layer and an N second buffer layer. Then, a P+ collector layer and a collector electrode are formed on the proton-irradiated surface. The distance from a position where the net doping concentration of the N+ first buffer layer is locally maximized to the interface between the P+ collector layer and the N second buffer layer is set to be in a range of 5 ?m to 30 ?m, both inclusively.Type: ApplicationFiled: November 18, 2011Publication date: March 15, 2012Applicant: FUJI ELECTRIC CO., LTD.Inventors: Michio NEMOTO, Haruo NAKAZAWA
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Patent number: 8084814Abstract: A semiconductor device is provided in which a semiconductor substrate can be prevented from being broken while elements can be prevented from being destroyed by a snap-back phenomenon. After an MOS gate structure is formed in a front surface of an FZ wafer, a rear surface of the FZ wafer is ground. Then, the ground surface is irradiated with protons and irradiated with two kinds of laser beams different in wavelength simultaneously to thereby form an N+ first buffer layer and an N second buffer layer. Then, a P+ collector layer and a collector electrode are formed on the proton-irradiated surface. The distance from a position where the net doping concentration of the N+ first buffer layer is locally maximized to the interface between the P+ collector layer and the N second buffer layer is set to be in a range of 5 ?m to 30 ?m, both inclusively.Type: GrantFiled: January 22, 2009Date of Patent: December 27, 2011Assignee: Fuji Electric Co., Ltd.Inventors: Michio Nemoto, Haruo Nakazawa
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Patent number: 8076173Abstract: A semiconductor substrate and a method of its manufacture has a semiconductor substrate having a carbon concentration in a range of 6.0×1015 to 2.0×1017 atoms/cm3, both inclusively. One principal surface of the substrate is irradiated with protons and then heat-treated to thereby form a broad buffer structure, namely a region in a first semiconductor layer where a net impurity doping concentration is locally maximized. Due to the broad buffer structure, lifetime values are substantially equalized in a region extending from an interface between the first semiconductor layer and a second semiconductor layer formed on the first semiconductor layer to the region where the net impurity doping concentration is locally maximized. In addition, the local minimum of lifetime values of the first semiconductor layer becomes high.Type: GrantFiled: January 31, 2011Date of Patent: December 13, 2011Assignee: Fuji Electric Co., Ltd.Inventor: Michio Nemoto
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Publication number: 20110186965Abstract: Reverse-conducting insulated gate bipolar transistor in which IGBT region and FWD region are integrated into a single body in a semiconductor substrate with a common active region is disclosed. MOS gate structure is on a first major surface side. Rear surface side structure is in a second major surface side of the semiconductor substrate and includes a plurality of recessed parts vertical to the second major surface, which are repeated periodically along the second major surface. A plurality of protruding parts are interposed between the recessed parts. Rear surface side structure includes p type collector region on a bottom surface of the recessed part, n type first field stop region at a position deeper than the collector region, n type cathode region on the top surface of the protruding part, and n type second field stop region in the protruding part at a position deeper than the cathode region.Type: ApplicationFiled: January 27, 2011Publication date: August 4, 2011Applicant: FUJI ELECTRIC SYSTEMS CO. LTD.Inventors: Michio NEMOTO, Souichi YOSHIDA
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Publication number: 20110163409Abstract: A TMBS diode is disclosed. In an active portion and a voltage withstanding structure portion of the diode, an end portion trench surrounds active portion trenches. An active end portion which is an outer circumferential side end portion of an anode electrode is in contact with conductive polysilicon inside the end portion trench. A guard trench is separated from the end portion trench and surrounds it. A field plate provided on an outer circumferential portion of the anode electrode is separated from the anode electrode, and contacts both part of a surface of an n-type drift layer in a mesa region between the end portion trench and the guard trench and the conductive polysilicon formed inside the guard trench. The semiconductor device is high in withstand voltage without injection of minority carriers, and electric field intensity of a trench formed in an end portion of an active portion is relaxed.Type: ApplicationFiled: January 4, 2011Publication date: July 7, 2011Applicant: C/O FUJI ELECTRIC SYSTEMS CO., LTDInventors: Tomonori MIZUSHIMA, Michio NEMOTO