Patents by Inventor Michio Numa

Michio Numa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7378899
    Abstract: A semiconductor integrated circuit according to the present invention comprises a circuit as a controlled object including an MOS transistor, wherein a control potential (at least one of a substrate potential and source potential) is to be controlled, a control signal generation circuit for generating a control signal with respect to the control potential based on an internal signal of the circuit as the controlled object, and a control potential control circuit for controlling the control potential (substrate potential/source potential) of the MOS transistor based on the control signal.
    Type: Grant
    Filed: October 2, 2006
    Date of Patent: May 27, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kaori Hatakeyama, Masaya Sumita, Keisuke Kishishita, Michio Numa
  • Publication number: 20070024344
    Abstract: A semiconductor integrated circuit according to the present invention comprises a circuit as a controlled object including an MOS transistor, wherein a control potential (at least one of a substrate potential and source potential) is to be controlled, a control signal generation circuit for generating a control signal with respect to the control potential based on an internal signal of the circuit as the controlled object, and a control potential control circuit for controlling the control potential (substrate potential/source potential) of the MOS transistor based on the control signal.
    Type: Application
    Filed: October 2, 2006
    Publication date: February 1, 2007
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Kaori Hatakeyama, Masaya Sumita, Keisuke Kishishita, Michio Numa
  • Patent number: 7123076
    Abstract: A semiconductor integrated circuit according to the present invention comprises a circuit as a controlled object including an MOS transistor, wherein a control potential (at least one of a substrate potential and source potential) is to be controlled, a control signal generation circuit for generating a control signal with respect to the control potential based on an internal signal of the circuit as the controlled object, and a control potential control circuit for controlling the control potential (substrate potential/source potential) of the MOS transistor based on the control signal.
    Type: Grant
    Filed: August 19, 2004
    Date of Patent: October 17, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kaori Hatakeyama, Masaya Sumita, Keisuke Kishishita, Michio Numa
  • Publication number: 20050047247
    Abstract: A semiconductor integrated circuit according to the present invention comprises a circuit as a controlled object including an MOS transistor, wherein a control potential (at least one of a substrate potential and source potential) is to be controlled, a control signal generation circuit for generating a control signal with respect to the control potential based on an internal signal of the circuit as the controlled object, and a control potential control circuit for controlling the control potential (substrate potential/source potential) of the MOS transistor based on the control signal.
    Type: Application
    Filed: August 19, 2004
    Publication date: March 3, 2005
    Inventors: Kaori Hatakeyama, Masaya Sumita, Keisuke Kishishita, Michio Numa