Patents by Inventor Michio Numata

Michio Numata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8832349
    Abstract: According to an aspect of an embodiment, a server system includes a service processor, a plurality of system boards and a plurality of crossbar boards connecting the system boards. The service processor includes a first notifier that notifies each of the crossbar boards of a crossbar board subjected to maintenance. The crossbar boards each include a first transmitter that, when notified by the service processor that the crossbar board subjected to maintenance is another crossbar board, generates a suspension packet for suspending packet transmission to the another crossbar board and transmits the suspension packet to each of the system boards. The system boards each include a suspender that, when receiving the suspension packet from the crossbar board, suspends packet transmission to the crossbar board subjected to maintenance.
    Type: Grant
    Filed: September 20, 2013
    Date of Patent: September 9, 2014
    Assignee: Fujitsu Limited
    Inventors: Michio Numata, Yasuhiro Kuroda
  • Patent number: 8639967
    Abstract: A controlling apparatus for controlling an information processing apparatus, the controlling apparatus includes a first controller including a first data transfer unit that communicates data between the information processing apparatus, and a first processing unit that generates a command to instruct the first data transfer unit to communicate data between the information processing apparatus, and a second controller including a second data transfer unit that communicates data between the information processing apparatus, and a second processing unit that generates a command to instruct the second data transfer unit to communicate data between the information processing apparatus.
    Type: Grant
    Filed: August 16, 2011
    Date of Patent: January 28, 2014
    Assignee: Fujitsu Limited
    Inventors: Tamaki Imakawa, Hitoshi Matsumori, Toshiharu Maekawa, Michio Numata, Satoru Sakai
  • Publication number: 20140025862
    Abstract: According to an aspect of an embodiment, a server system includes a service processor, a plurality of system boards and a plurality of crossbar boards connecting the system boards. The service processor includes a first notifier that notifies each of the crossbar boards of a crossbar board subjected to maintenance. The crossbar boards each include a first transmitter that, when notified by the service processor that the crossbar board subjected to maintenance is another crossbar board, generates a suspension packet for suspending packet transmission to the another crossbar board and transmits the suspension packet to each of the system boards. The system boards each include a suspender that, when receiving the suspension packet from the crossbar board, suspends packet transmission to the crossbar board subjected to maintenance.
    Type: Application
    Filed: September 20, 2013
    Publication date: January 23, 2014
    Applicant: FUJITSU LIMITED
    Inventors: Michio NUMATA, Yasuhiro KURODA
  • Publication number: 20120047397
    Abstract: A controlling apparatus for controlling an information processing apparatus, the controlling apparatus includes a first controller including a first data transfer unit that communicates data between the information processing apparatus, and a first processing unit that generates a command to instruct the first data transfer unit to communicate data between the information processing apparatus, and a second controller including a second data transfer unit that communicates data between the information processing apparatus, and a second processing unit that generates a command to instruct the second data transfer unit to communicate data between the information processing apparatus.
    Type: Application
    Filed: August 16, 2011
    Publication date: February 23, 2012
    Applicant: Fujitsu Limited
    Inventors: Tamaki Imakawa, Hitoshi Matsumori, Toshiharu Maekawa, Michio Numata, Satoru Sakai
  • Patent number: 8020048
    Abstract: A POST management apparatus for managing a POST of an SB in a partition which operates in units of an OS using the CPU of the SB as a resource accesses the storage area storing the POST of the SB so as to perform read/write operation and to acquire/recognize the individual information on the SB and the version number information of the POST, transmits the POST of a predetermined version number according to at least one of the individual information and the version number information, and manages the version number of the POST so that the version numbers of the POSTs used in the SBs in units of a partition coincide with each other.
    Type: Grant
    Filed: July 29, 2008
    Date of Patent: September 13, 2011
    Assignee: Fujitsu Limited
    Inventor: Michio Numata
  • Publication number: 20080288824
    Abstract: A POST management apparatus for managing a POST of an SB in a partition which operates in units of an OS using the CPU of the SB as a resource accesses the storage area storing the POST of the SB so as to perform read/write operation and to acquire/recognize the individual information on the SB and the version number information of the POST, transmits the POST of a predetermined version number according to at least one of the individual information and the version number information, and manages the version number of the POST so that the version numbers of the POSTs used in the SBs in units of a partition coincide with each other.
    Type: Application
    Filed: July 29, 2008
    Publication date: November 20, 2008
    Applicant: FUJITSU LIMITED
    Inventor: Michio NUMATA
  • Patent number: 6326824
    Abstract: An initial value generation circuit generates an initial value taking into consideration the a time delay when a signal is transmitted through the signal wires between a pilot device and other devices, and a processing delay caused in respective devices. When a device receives a system synchronizing signal form another device, the device sets an initial value in a counter. Thereby, the counter value of a counter in a pilot device and counter values of counters in the other devices are made to coincide with each other.
    Type: Grant
    Filed: July 27, 2000
    Date of Patent: December 4, 2001
    Assignee: Fujitsu Limited
    Inventors: Koji Hosoe, Jun Funaki, Toshiyuki Shimizu, Michio Numata