Abstract: In a semiconductor device according to an embodiment, a thickness of a semiconductor layer of an SOI substrate on which a field effect transistor constituting an analog circuit is formed is set to 2 nm or more and 24 nm or less.

Abstract: In a semiconductor device according to an embodiment, a thickness of a semiconductor layer of an SOI substrate on which a field effect transistor constituting an analog circuit is formed is set to 2 nm or more and 24 nm or less.

Abstract: In a semiconductor device according to an embodiment, a thickness of a semiconductor layer of an SOI substrate on which a field effect transistor constituting an analog circuit is formed is set to 2 nm or more and 24 nm or less.

Abstract: To contribute to increase data transmission rate for server management without increasing load during normal operation. A semiconductor integrated circuit includes: a central processing unit; an external memory interface circuit; a network interface circuit; an image processing unit; and a data compression unit. The image processing unit performs image processing in response to an input from an external bus, the image processing unit is coupled to an external memory interface circuit through a dedicated internal bus, and the image processing unit stores an image data into an external memory via the dedicated internal bus. The compression unit is coupled to the image processing unit and is capable of compressing the image data supplied from the image processing unit.

Abstract: The present invention provides a data processor operating in a card host in such a manner as to easily eliminate access errors attributable to propagation delays of a clock signal and data. A memory card interface controller transmits a clock signal to a memory card to acquire read data therefrom in synchronism with the clock signal, the memory card interface controller being switchable between a raising edge and a falling edge of the clock signal when acquiring the read data in synchronous relation with the clock signal. It is possible to adjust a timing of read data acquisition by a half cycle of the clock signal. The memory card interface controller may be switched between different frequencies of the clock signal. Additional switching of frequencies provides more flexibility for timing adjustment.