Abstract: In order to rapidly determine a most likely code word at a decoder provided in a digital data transmission system using block codes or convolutional codes for the purposes of combating a noisy channel environment, an adaptively controllable threshold is introduced so as to discriminate a largest metric with a small amount of computations. The metric is the measure of closeness of a signal transmitted to the decoder to one of plural code words previously stored in the decoder. A counter counts the number of metrics each exceeding the threshold, and informs a controller of the count result, if the count result is more than one, the controller raises the threshold, on the contrary, if the count result is zero then the controller lowers the threshold, both are performed in an effort to narrow down one metric in excess of the threshold. The threshold thus adaptively controlled is compared with each of plural metrics. If the count result becomes one, it implies that the largest metric has been determined.

Abstract: Sequentially decoding a plurality of symbol sets of an incoming data sequence with less amount of computation in an application wherein paths in a code tree do not occur equiprobably is disclosed. A code tree is previously memorized which comprises a plurality of paths defined by a plurality of sequences of nodes. A pointer generator is provided for generating a pointer that defines a node that specifies a path in the code tree. A plurality of branch metric generators each generates a metric of a branch which forms part of a path and which is to be examined with a corresponding symbol set of the incoming data sequence. Further, a plurality of path metric generators are provided which respectively receive the branch metrics from the plurality of branch metric generators and respectively generate path metrics using the branch metrics.

Abstract: An adder circuit can perform of two integers respective consisted of n=k m bits at high speed with a smaller scale circuit than that of an adder circuit employing a carry look ahead circuit. The adder circuit includes m in number of k-bit adding circuits connected in serial connection in such a manner that an carry output in a preceding digit is supplied to a carry input in a following digit, m in number of carry propagation alarm circuits provided corresponding to respective of m in number of k-bit adding means, for outputting carry propagation alarm signal only when carry input of corresponding adding means is propagated to a carry output, and OR circuit for performing OR for performing OR operation of the m in number of carry propagation alarm signals for generating a carry alarm signal, for leading a fixed result of addition from a final digit of the adding means in serial connection after extinction of generation of the carry alarm signal.

Abstract: In order to rapidly determine a most likely code word at a decoder provided in a digital data transmission system using block codes or convolutional codes for the purposes of combating a noisy channel environment, an adaptively controllable threshold is introduced so as to discriminate a largest metric with a small amount of computations. The metric is the measure of closeness of a signal transmitted to the decoder to one of plural code words previously stored in the decoder. A counter counts the number of metrics each exceeding the threshold, and informs a controller of the count result, if the count result is more than one, the controller raises the threshold, on the contrary, if the count result is zero then the controller lowers the threshold, both are performed in an effort to narrow down one metric in excess of the threshold. The threshold thus adaptively controlled is compared with each of plural metrics. If the count result becomes one, it implies that the largest metric has been determined.

Abstract: Sequentially decoding a plurality of symbol sets of an incoming data sequence with less amount of computation in an application wherein paths in a code tree do not occur equiprobably is disclosed. A code tree is previously memorized which comprises a plurality of paths defined by a plurality of sequences of nodes. A pointer generator is provided for generating a pointer that defines a node that specifies a path in the code tree. A plurality of branch metric generators each generates a metric of a branch which forms part of a path and which is to be examined with a corresponding symbol set of the incoming data sequence. Further, a plurality of path metric generators are provided which respectively receive the branch metrics from the plurality of branch metric generators and respectively generate path metrics using the branch metrics.

Abstract: To provide a method of generating internal crypto-keys to be set initially in a feedback-shift-registers of a pseudo-random-sequence generator of a stream cipher system with sufficient security and sufficiently high speed as well, the method comprises: a step of outputting m sets of first conversion results, obtaining i-th set of the first conversion results by processing (i−1)-th set of the first conversion results with a first one-way-function; a step of outputting m sets of second conversion results, obtaining i-th set of the second conversion results by processing (i−1)-th sets of the second conversion results with a second one-way function; and a step of outputting j-th internal crypto-key by XORing j-th set of the first conversion results and (m−j+1)-th set of the second conversion results.

Abstract: When a charging lid is manually opened or closed, a rotatable shaft is rotated thereby. At this time, a second rotary member rotates about the rotatable shaft and moves axially along the rotatable shaft. Balls are released from engagement recesses defined in the second rotary member, disengaging a first rotary member from the second rotary member. The charging lid can thus easily manually be opened or closed. When the rotatable shaft is rotated a given angle, a sensor detects the angular displacement of the rotatable shaft and outputs a detected signal. In response to the detected signal, a motor is energized to rotate the rotatable shaft to forcibly open or close the charging lid.

Abstract: A register 205 of each pseudorandom number generating circuit 101 takes in and holds a state data composed of a plurality of bits in synchronism with a clock pulse of a clock signal. Function generator circuits 2021 and 2022 output data each composed of a plurality of bits correspondingly to the state data held in the register 205. A selector 203 selects a specific bit of either one of the two data output from the function generator circuits on the basis of a pseudorandom number Xi−1 generated by a preceding one of the pseudorandom number generating circuits and outputs it as a pseudorandom number Xi. On the other hand, another selector 206 selects one of the data output from the function generator circuits, except the specific bit thereof, according to the pseudorandom number Xi−1 generated by the preceding pseudorandom number generating circuit and supplies the selected data to the register 205 as the state data.

Abstract: A generator 101 produces randomly an integer A.sub.1 which satisfies 0.ltoreq.A<(P.sub.1 -1)(P.sub.2 -1) . . . (P.sub.m -1), in synchronism With a clock pulse applied via an input terminal 180, where each of P.sub.1, P.sub.2, . . . P.sub.m is a prime number equal to or more than 2. First calculating means 4 calculates an integer X, whose probability of being a prime number is high, using the integer A based on equation X=a.sub.1 (P.sub.1 P.sub.2. . . P.sub.m /P.sub.1)B.sub.1 +a.sub.2 (P.sub.1 P.sub.2. . . P.sub.m /P.sub.2)B.sub.2 +a.sub.m (P.sub.1 P.sub.2. . . P.sub.m /P.sub.m)B.sub.m (mod P.sub.1 P.sub.2. . . P.sub.m). In this case, a.sub.k (k=1, 2, . . . , m) is an integer which satisfies congruence equation a.sub.k (P.sub.1 P.sub.2. . . P.sub.m /P.sub.k)=1 (mod P.sub.k), while B.sub.k represents {A mod (P.sub.k -1)}+1. An adder 107 outputs the integer X as an integer with a predetermined number of bits.

Abstract: To provide an apparatus for generating pseudo-random numbers at a high speed with sufficient cryptographical security, the apparatus comprises: a T-ary counter (101) for generating a count number from 0 to T-1 cyclically by incrementing the count number in synchronization with a clock signal; a modulus memory (103) for outputting a prime number read out from T prime numbers prepared therein according to a value of the count number; an n-bit register (102) for registering and outputting an n-bit value in synchronization with the clock signal; an expanded affine transformation circuit (104) for outputting an intermediate number, by performing expanded affine transformation of the n-bit value registered in the n-bit register (102) according to the prime number, the n-bit value being revised with the intermediate number in synchronization with the clock signal; and a demagnification circuit (105) for outputting certain s bits of the intermediate number as one of the pseudo-random numbers in synchronization with t

Abstract: A pseudorandom number sequence generator comprises a bidirectional shift register arranged to be loaded with a multi-bit sequence. The shift register is responsive to an ith clock pulse and an ith direction control bit for shifting the multi-bit sequence in one of two directions, delivering an ith output bit and receiving an ith input bit. The multi-bit sequence successively defines one of nodes of an Eulerian graph connected by branches. A feedback circuit is connected to the shift register for converting a set of input data to a set of output data. The input data comprises a multi-bit sequence stored in the shift register in response to an (i+1)th clock pulse, the ith output bit and the ith direction control bit and the output data comprises an (i+1)th input bit and an (i+1)th direction control bit.

Abstract: In a product cipher apparatus, a permutation is performed upon plaintext or ciphertext to generate a first message. At least two successive substitutions are performed upon the first message to generate a second message, and the same permutation is performed upon the second message to generate a third message. The successive substitutions and the permutation are repeatedly performed upon the third message to obtain ciphertext or plaintext.

Abstract: ELT transformation circuits 101.sub.1 to 101.sub.m are preliminarily supplied with ELT transformation parameters a.sub.i, b.sub.i, and p.sub.i (i=1, 2, . . . , m). When a plaintext of n bits long is supplied to the ELT transformation circuit 101.sub.1 via an input terminal 104, the ELT transformation circuit 101.sub.1 carries out ELT transformation on the plaintext by the use of ELT transformation parameters a.sub.1, b.sub.1, and p.sub.1 supplied from an input terminal 105.sub.1. An enciphering circuit 102.sub.1 enciphers an n/2-bit input with reference to a cryptographic key K.sub.1 from an input terminal 106.sub.1. Supplied with two n-bit inputs, an exclusive-OR circuit 103.sub.1 carries out an exclusive-OR operation between every corresponding bits of the same order. Subsequently, similar operation as mentioned above is repeated. The ELT transformation circuit 101.sub.m at a final stage delivers a ciphertext to an output terminal 107.

Abstract: The invention provides a public-key cryptographic apparatus which does not leak information regarding a plaintext and can prevent an increase in block length. A quadratic residue calculation circuit calculates a residue when the square of the lower n-1 bits of the plaintext of n bits is divided by public-key, and an exclusive OR circuit calculates an exclusive OR of the least significant bit of a result of the calculation and the most significant bit of the plaintext. Then, public-key encipherment such as the RSA cryptosystem or a modified Rabin cryptosystem is performed twice repetitively for totaling n bits of the output of exclusive OR circuit and the lower n-1 bits of plaintext by public-key enciphering circuits so as to make it impossible to estimate the most significant bit of the plaintext from the ciphertext.

Abstract: A pseudorandom number generator which uses linear feedback shift registers and a nonlinear function circuit and can make the conditioned output distribution of generated pseudorandom numbers uniform even if the conditioned output distribution of the nonlinear function circuit has some deviation. The generator has a shift register to which the output of the nonlinear function circuit is inputted as a serial input, an initial value setting circuit for setting random initial values to the linear feedback shift registers and the shift registers, and an adder for adding predetermined bits of the parallel outputs of the register and outputting a pseudorandom number stream. The generator can be used to generate a cryptogram which cannot be deciphered by the correlation attack method.

Abstract: A hardware arrangement is provided for transforming plaintext into corresponding ciphertext. The plaintext includes a plurality of words each having a predetermined bit length. The hardware arrangement sequentially acquires the words and exhibits a predetermined number of arithmetic operations on the word acquired. Each of the arithmetic operations includes a plurality of arithmetic processes. The hardware arrangement outputs an enciphered word therefrom when completing the predetermined number of arithmetic operations. A selector is arranged to receive two inputs and selectively output one of the two inputs. One of the two inputs corresponds to the word acquired. A multiplier is coupled to receive the output of the selector. The multiplier multiplies the output of the selector by a multiplier and outputs a product therefrom. An adder is coupled to receive the product. The adder adds the product and an addend and then outputs a sum.

Abstract: In a sequential decoding apparatus, a sequential decoder performs sequential decoding on convolutional code symbols stored in a data buffer according to the maximum likelihood algorithm. When the buffer is overflowed due to random noise, the sequential decoder skips a portion of the stored symbols, clears its internal state and initiates a stepwise decoding on symbols of newly arrival. A sync detector detects that a count of symbols that have been decoded after the occurrence of the overflow is lower or higher than a predetermined value. If the overflow condition still exists following the stepwise decoding, a portion of the stored symbols is further skipped and the stepwise decoding is repeated. If the overflow condition ceases to exist and if the decoded symbol count is still lower than the predetermined value, the symbol skipping and stepwise decoding are repeated until it becomes higher than the predetermined value to cause the sequential decoder to resume normal operation.

Abstract: An encrypting method for producing a code which cannot be deciphered by an eavesdropper. The encrypting method does not require the bit length of input information to be increased when the information is converted into a cryptogram. The encrypting method uses a prior art encryptor and decryptor when it determines that the input information is small enough to not overrun the bit length when encrypted, and a bit-length preservation encryptor and decryptor when the input information will overrun the bit length when encrypted.

Abstract: For use in decoding received code symbols corresponding to original code symbols consisting of original information symbols and original redundancy symbols and comprising a sequential decode controller (45) responsive to the received code symbols for producing a sequence of presumed information symbols corresponding to the respective original information symbols, an encoder replica (46, 47) responsive to the presumed information symbols for producing presumed code symbols consisting of the presumed information symbols and presumed redundancy symbols corresponding to the respective original redundancy symbols, and a likelihood calculator (48) for calculating likelihoods which the presumed code symbols have relative to the respective received code symbols, a decoder comprises a position counter (61) for counting position counts for the respective presumed information symbols in the sequence and a modifier (81) for giving a predetermined value, such as zero, to the likelihoods calculated for the respective presu

Abstract: In an encoder replica of a decoder for an input code sequence which corresponds to a code symbol sequence comprising an information symbol sequence and a redundancy bit sequence, a one-bit memory (46) successively memorizes consecutive bits of the input code sequence as memorized bits. An output circuit (62) delivers replica output bits in bit series to a sequential decode controller (43) in response to the memorized bits. In response to the memorized bits and a control signal produced by the controller in response to the input code sequence and the replica output bits, the encoder replica decodes the input code sequence into a reproduction of the information symbol sequence. Preferably, the output circuit is controlled by a position counter (64) giving separate indication of bits corresponding in the input code sequence to the information symbol sequence and of bits corresponding in the input code sequence to the redundancy bit sequence.