Patents by Inventor Michio Tamate
Michio Tamate has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230060703Abstract: Provided is a semiconductor module having a P-side arm circuit and an N-side arm circuit. The semiconductor module comprises: a P terminal on a high-voltage side; an N terminal on a low-voltage side; a plurality of wiring patterns separated from each other; and a transistor and a diode connected in parallel in each of the circuits, wherein the plurality of wiring patterns include a first wiring pattern, a second wiring pattern, and a third wiring pattern, the P terminal is connected to the first wiring pattern, the N terminal is connected to the second wiring pattern, an anode electrode of the diode of the N-side arm circuit is arranged above the second wiring pattern and is connected to the second wiring pattern, and an anode electrode of the diode of the P-side arm circuit is arranged above the third wiring pattern and is connected to the third wiring pattern.Type: ApplicationFiled: June 20, 2022Publication date: March 2, 2023Inventors: Tamiko ASANO, Michio TAMATE
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Publication number: 20220406690Abstract: A semiconductor device includes: an insulated circuit substrate including first and second conductive layers on a top surface side; a first semiconductor chip mounted on the first conductive layer; a second semiconductor chip mounted on the second conductive layer; a printed circuit board including a first lower-side wiring layer arranged to be opposed to the first semiconductor chip, and a second lower-side wiring layer arranged to be opposed to the second semiconductor chip, the printed circuit board being provided with a curved part curved toward the insulated circuit substrate; a first connection member arranged to connect the first semiconductor chip with the first lower-side wiring layer; a second connection member arranged to connect the second semiconductor chip with the second lower-side wiring layer; and a third connection member arranged to connect the first conductive layer with the second lower-side wiring layer at the curved part.Type: ApplicationFiled: April 28, 2022Publication date: December 22, 2022Applicant: FUJI ELECTRIC CO., LTD.Inventors: Motohito HORI, Yoshinari IKEDA, Akio TOBA, Michio TAMATE, Ikuya SATO
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Patent number: 11506701Abstract: The electromagnetic noise of a semiconductor device is conveniently evaluated, and the electromagnetic noise of an apparatus equipped with the semiconductor device is estimated. An evaluation method is provided which includes causing one of a first device and a second device of a semiconductor device to perform a switching operation, the semiconductor device comprising the first device and second device connected in series and a third device and a fourth device connected to each other in series and connected parallel to a series circuit of the first device and second device; measuring voltage variation occurring between the third device and the fourth device during the switching operation; and outputting an evaluation benchmark for electromagnetic noise of the semiconductor device, based on the voltage variation.Type: GrantFiled: November 25, 2019Date of Patent: November 22, 2022Assignee: FUJI ELECTRIC CO., LTD.Inventors: Miwako Fujita, Michio Tamate, Tamiko Asano, Yuhei Suzuki, Ryu Araki
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Patent number: 11162993Abstract: The radiated noise of a semiconductor device is conveniently evaluated, and the radiated noise of an apparatus equipped with the semiconductor device is estimated. An evaluation method including: making a semiconductor device that is connected parallel to a load by a load cable, perform a switching operation; measuring common-mode current flowing through the load cable during the switching operation; and outputting an evaluation benchmark for radiated noise based on the common-mode current, and an evaluation apparatus are provided.Type: GrantFiled: January 29, 2019Date of Patent: November 2, 2021Assignee: FUJI ELECTRIC CO., LTD.Inventors: Hiroki Katsumata, Michio Tamate, Miwako Fujita, Tamiko Asano, Yuhei Suzuki, Takashi Kaimi, Yuta Sunasaka, Tadanori Yamada, Ryu Araki, Bao Cong Hiu
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Patent number: 11143691Abstract: The radiated noise of a semiconductor device is conveniently evaluated, and the radiated noise of an apparatus equipped with the semiconductor device is estimated. An evaluation method and an evaluation apparatus are provided, including: causing a semiconductor device to perform a switching operation; measuring voltage variation occurring between main terminals of the semiconductor device during the switching operation; and outputting an evaluation benchmark for radiated noise of the semiconductor device based on the voltage variation. The outputting the evaluation benchmark may include calculating the voltage variation in the semiconductor device for each frequency component as the evaluation benchmark.Type: GrantFiled: January 29, 2019Date of Patent: October 12, 2021Assignee: FUJI ELECTRIC CO., LTD.Inventors: Hiroki Katsumata, Michio Tamate, Miwako Fujita, Tamiko Asano, Yuhei Suzuki, Takashi Kaimi, Yuta Sunasaka, Tadanori Yamada, Ryu Araki, Bao Cong Hiu
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Publication number: 20200217884Abstract: The electromagnetic noise of a semiconductor device is conveniently evaluated, and the electromagnetic noise of an apparatus equipped with the semiconductor device is estimated. An evaluation method is provided which includes causing one of a first device and a second device of a semiconductor device to perform a switching operation, the semiconductor device comprising the first device and second device connected in series and a third device and a fourth device connected to each other in series and connected parallel to a series circuit of the first device and second device; measuring voltage variation occurring between the third device and the fourth device during the switching operation; and outputting an evaluation benchmark for electromagnetic noise of the semiconductor device, based on the voltage variation.Type: ApplicationFiled: November 25, 2019Publication date: July 9, 2020Inventors: Miwako FUJITA, Michio TAMATE, Tamiko ASANO, Yuhei SUZUKI, Ryu ARAKI
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Publication number: 20190170807Abstract: The radiated noise of a semiconductor device is conveniently evaluated, and the radiated noise of an apparatus equipped with the semiconductor device is estimated. An evaluation method and an evaluation apparatus are provided, including: causing a semiconductor device to perform a switching operation; measuring voltage variation occurring between main terminals of the semiconductor device during the switching operation; and outputting an evaluation benchmark for radiated noise of the semiconductor device based on the voltage variation. The outputting the evaluation benchmark may include calculating the voltage variation in the semiconductor device for each frequency component as the evaluation benchmark.Type: ApplicationFiled: January 29, 2019Publication date: June 6, 2019Inventors: Hiroki KATSUMATA, Michio TAMATE, Miwako FUJITA, Tamiko ASANO, Yuhei SUZUKI, Takashi KAIMI, Yuta SUNASAKA, Tadanori YAMADA, Ryu ARAKI, Bao Cong HIU
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Publication number: 20190170798Abstract: The radiated noise of a semiconductor device is conveniently evaluated, and the radiated noise of an apparatus equipped with the semiconductor device is estimated. An evaluation method including: making a semiconductor device that is connected parallel to a load by a load cable, perform a switching operation; measuring common-mode current flowing through the load cable during the switching operation; and outputting an evaluation benchmark for radiated noise based on the common-mode current, and an evaluation apparatus are provided.Type: ApplicationFiled: January 29, 2019Publication date: June 6, 2019Inventors: Hiroki KATSUMATA, Michio TAMATE, Miwako FUJITA, Tamiko ASANO, Yuhei SUZUKI, Takashi KAIMI, Yuta SUNASAKA, Tadanori YAMADA, Ryu ARAKI, Bao Cong HIU
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Patent number: 9632564Abstract: In a power supply device, the bridge circuit is configured by connecting, in parallel, a plurality of series circuits of an inverse-parallel connection circuit of a semiconductor switch and a diode. A control unit controls switching of a semiconductor switch so that a voltage v between AC terminals becomes zero voltage in equal periods ? before and after a center point shifted from one zero crossing point in one cycle of the input current by a compensation period (angle) ? calculated from a voltage applied to a resonance circuit constituted by the power receiving coil and a resonance capacitor Cr and an induced voltage of the power receiving coil, and becomes a positive-negative voltage whose peak value is the voltage Vo between DC terminals in other periods.Type: GrantFiled: June 10, 2014Date of Patent: April 25, 2017Assignees: CENTRAL JAPAN RAILWAY COMPANY, FUJI ELECTRIC CO., LTD.Inventors: Toshiaki Murai, Yoshiyasu Hagiwara, Tadashi Sawada, Masayuki Tobikawa, Ayako Saga, Michio Tamate, Koji Maruyama, Tomotaka Nishijima
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Patent number: 9608539Abstract: In a power supply device the bridge circuit is configured such that a plurality of series circuits of two inverse parallel connection circuits of a semiconductor switch and a diode are connected in parallel. The power supply device includes a control unit configured to control the semiconductor switch such that a voltage between AC terminals of the bridge circuit becomes a zero voltage only during a prescribed time period before and after two zero crossing points in one cycle of the input current and such that the voltage becomes a positive-negative voltage in which the output voltage is a peak current value during other time periods. Consequently, a power factor of the power receiving circuit is improved and a loss of an entire device is inhibited, and a size and a cost of the entire device may be reduced.Type: GrantFiled: March 7, 2014Date of Patent: March 28, 2017Assignees: CENTRAL JAPAN RAILWAY COMPANY, FUJI ELECTRIC CO., LTD.Inventors: Ayako Ichinose, Michio Tamate, Koji Maruyama, Tomotaka Nishijima
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Publication number: 20140372780Abstract: In a power supply device, the bridge circuit is configured by connecting, in parallel, a plurality of series circuits of an inverse-parallel connection circuit of a semiconductor switch and a diode. A control unit controls switching of a semiconductor switch so that a voltage v between AC terminals becomes zero voltage in equal periods ? before and after a center point shifted from one zero crossing point in one cycle of the input current by a compensation period (angle) ? calculated from a voltage applied to a resonance circuit constituted by the power receiving coil and a resonance capacitor Cr and an induced voltage of the power receiving coil, and becomes a positive-negative voltage whose peak value is the voltage Vo between DC terminals in other periods.Type: ApplicationFiled: June 10, 2014Publication date: December 18, 2014Applicants: CENTRAL JAPAN RAILWAY COMPANY, FUJI ELECTRIC CO., LTD.Inventors: Toshiaki MURAI, Yoshiyasu HAGIWARA, Tadashi SAWADA, Masayuki TOBIKAWA, Ayako SAGA, Michio TAMATE, Koji MARUYAMA, Tomotaka NISHIJIMA
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Publication number: 20140292092Abstract: In a power supply device the bridge circuit is configured such that a plurality of series circuits of two inverse parallel connection circuits of a semiconductor switch and a diode are connected in parallel. The power supply device includes a control unit configured to control the semiconductor switch such that a voltage between AC terminals of the bridge circuit becomes a zero voltage only during a prescribed time period before and after two zero crossing points in one cycle of the input current and such that the voltage becomes a positive-negative voltage in which the output voltage is a peak current value during other time periods. Consequently, a power factor of the power receiving circuit is improved and a loss of an entire device is inhibited, and a size and a cost of the entire device may be reduced.Type: ApplicationFiled: March 7, 2014Publication date: October 2, 2014Applicants: FUJI ELECTRIC CO., LTD., CENTRAL JAPAN RAILWAY COMPANYInventors: Ayako ICHINOSE, Michio TAMATE, Koji MARUYAMA, Tomotaka NISHIJIMA
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Patent number: 8786314Abstract: A contactless power transfer system, including a coil configured to supply or receive power contactlessly via magnetic coupling, a bridge circuit having two direct current (DC) terminals and two alternating current (AC) terminals, and a smoothing capacitor connected between the DC terminals. A load is connectable to either end of the smoothing capacitor. One of the AC terminals is connected to one end of the coil via a first capacitor. The other of the AC terminals is connected to the other end of the coil. The bridge circuit includes two serially-connected circuits each having upper and lower arms, each arm having a semiconductor switch and a diode in reverse parallel connection. A second capacitor is connected in parallel to the semiconductor switch of an upper arm, or of a lower arm, or to two semiconductor switches respectively of an upper arm and of a lower arms, of the bridge circuit.Type: GrantFiled: November 17, 2011Date of Patent: July 22, 2014Assignee: Fuji Electric Co., Ltd.Inventors: Kouji Maruyama, Akio Toba, Ayako Ichinose, Michio Tamate
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Publication number: 20120127765Abstract: A contactless power transfer system, including a coil configured to supply or receive power contactlessly via magnetic coupling, a bridge circuit having two direct current (DC) terminals and two alternating current (AC) terminals, and a smoothing capacitor connected between the DC terminals. A load is connectable to either end of the smoothing capacitor. One of the AC terminals is connected to one end of the coil via a first capacitor. The other of the AC terminals is connected to the other end of the coil. The bridge circuit includes two serially-connected circuits each having upper and lower arms, each arm having a semiconductor switch and a diode in reverse parallel connection. A second capacitor is connected in parallel to the semiconductor switch of an upper arm, or of a lower arm, or to two semiconductor switches respectively of an upper arm and of a lower arms, of the bridge circuit.Type: ApplicationFiled: November 17, 2011Publication date: May 24, 2012Applicant: FUJI ELECTRIC CO., LTD.Inventors: Kouji MARUYAMA, Akio Toba, Ayako Ichinose, Michio Tamate