Abstract: An operational amplifier comprises an input stage, an output stage, and an intermediate circuitry connected between the input stage and the output stage. The operational amplifier may be biased between a high voltage line and a low voltage line. The input stage includes at least an amplifier circuit. The intermediate circuitry comprises at least a first pair of a first transistor and a first constant current source, both of which are connected in series to each other between the high voltage line and the low voltage line. The first pair may be adjacent to the output stage. A first intermediate point between the first transistor and the first constant current source may be connected to the output stage. At least a second pair of a second transistor and a second constant current source is provided, both of which are connected in series to each other between the high voltage line and the low voltage line. The second pair may be in parallel to the first pair and may be adjacent to the input stage.

Abstract: An analog input signal current is split into a tree form. Hierarchical subtraction process for subtracting a comparison reference current is performed in each current path in the tree structure. At the final stage of the tree structure, the current is compared with a reference current to obtain a digital signal on the basis of results of comparison.

Abstract: A first field effect transistor has a drain electrode connected to a first current input terminal of a first current mirror circuit and a gate electrode connected to a first voltage input terminal which is supplied with a first voltage input terminal. A second field effect transistor has a drain electrode connected to a first current output terminal of the first current mirror circuit and a gate electrode connected to a second voltage input terminal which is supplied with a second input voltage. A second current mirror circuit has a second current input terminal connected to the first current output terminal and a second current output terminal connected to a power terminal through a resistor and to a voltage output terminal which is supplied with an output voltage. A comparator may include third and fourth current mirror circuits instead of the first and the second field effect transistors.

Abstract: Current output terminals of first and second current mirror circuits are connected. An input terminal of a third current mirror circuit is connected to a node of the current output terminals of the first and second current mirror circuits. A load circuit is connected between a current output terminal of the third current mirror circuit and a first voltage. An output terminal is connected to the load circuit. First and second currents to be compared with each other are supplied to current input terminal of the first and second current mirror circuits.

Abstract: An operational amplifier includes a transistor differential pair having a common source terminal which is coupled to a first power supply terminal through a first current source circuit. A first transistor is provided which has a gate coupled to a first input terminal of the transistor differential pair, a source coupled to a first output of the transistor differential pair, and a drain coupled to a first output terminal. A second current source circuit is coupled between the first power supply terminal and the drain of the first transistor. A second transistor has a gate coupled to a second input terminal of the transistor differential pair, a source coupled to a second output of the transistor differential pair, and a drain coupled to a second output terminal. A third current source circuit is coupled between the first power supply terminal and the drain of the second transistor. A fourth current source circuit is coupled between the source of the first transistor and the second power supply terminal.

Abstract: A serial-parallel type A/D converter comprises first and second circuit blocks which are connected serially to operate in pipe lining. An input analogue signal is converted to a digital signal having highest significant bits at the first circuit block, and an analogue signal obtained by subtracting an analogue signal equal in value to the digital signal from the input analogue signal is converted at the second circuit block. The second circuit block is a recursive circuit block in which A/D converting operation is carried out for a plurality of cycles at the timing of several times faster than that of the first circuit block.