Patents by Inventor Michiru Nakane

Michiru Nakane has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11751391
    Abstract: A process for building a 3-Dimensional NOR memory array avoids the challenge of etching a conductor material that is aimed at providing local word lines at a fine pitch. The process defines the local word lines between isolation shafts that may be carried out at a lower aspect ratio than would be required for etching the conductor material.
    Type: Grant
    Filed: July 21, 2021
    Date of Patent: September 5, 2023
    Assignee: SUNRISE MEMORY CORPORATION
    Inventors: Vinod Purayath, Yosuke Nosho, Shohei Kamisaka, Michiru Nakane, Eli Harari
  • Publication number: 20230247831
    Abstract: A process for building a 3-Dimensional NOR memory array avoids the challenge of etching a conductor material that is aimed at providing local word lines at a fine pitch. The process defines the local word lines between isolation shafts that may be carried out at a lower aspect ratio than would be required for etching the conductor material.
    Type: Application
    Filed: July 21, 2021
    Publication date: August 3, 2023
    Inventors: Vinod Purayath, Yosuke Nosho, Shohei Kamisaka, Michiru Nakane, Eli Harari
  • Publication number: 20220028886
    Abstract: A process for building a 3-Dimensional NOR memory array avoids the challenge of etching a conductor material that is aimed at providing local word lines at a fine pitch. The process defines the local word lines between isolation shafts that may be carried out at a lower aspect ratio than would be required for etching the conductor material.
    Type: Application
    Filed: July 21, 2021
    Publication date: January 27, 2022
    Inventors: Vinod Purayath, Yosuke Nosho, Shohei Kamisaka, Michiru Nakane, Eli Harari