Patents by Inventor Michita FUJII

Michita FUJII has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Memory system
    Patent number: 12461686
    Abstract: A memory system includes a nonvolatile memory that stores table data and a memory controller for writing and reading data to and from the nonvolatile memory. The memory controller includes a volatile memory that can be in either a retention state during which power is supplied thereto or a power down state during which the power supplied thereto is cut off, a timer that measures elapsed time starting from when the memory system transitions to the low power state, and a register in which previously measured elapsed times are stored, and in which a current measured elapsed time is stored when the memory system wakes up from the low power state. The controller controls the transitioning of the volatile memory from the retention state to the power down state, if the measured elapsed time is greater than a threshold value, which is calculated based on the previously measured elapsed times.
    Type: Grant
    Filed: April 24, 2023
    Date of Patent: November 4, 2025
    Assignee: Kioxia Corporation
    Inventors: Tasuku Kobayashi, Daisuke Uchida, Michita Fujii
  • MEMORY SYSTEM
    Publication number: 20230259307
    Abstract: A memory system includes a nonvolatile memory that stores table data and a memory controller for writing and reading data to and from the nonvolatile memory. The memory controller includes a volatile memory that can be in either a retention state during which power is supplied thereto or a power down state during which the power supplied thereto is cut off, a timer that measures elapsed time starting from when the memory system transitions to the low power state, and a register in which previously measured elapsed times are stored, and in which a current measured elapsed time is stored when the memory system wakes up from the low power state. The controller controls the transitioning of the volatile memory from the retention state to the power down state, if the measured elapsed time is greater than a threshold value, which is calculated based on the previously measured elapsed times.
    Type: Application
    Filed: April 24, 2023
    Publication date: August 17, 2023
    Inventors: Tasuku KOBAYASHI, Daisuke UCHIDA, Michita FUJII
  • Memory system
    Patent number: 11662945
    Abstract: A memory system includes a nonvolatile memory that stores table data and a memory controller for writing and reading data to and from the nonvolatile memory. The memory controller includes a volatile memory that can be in either a retention state during which power is supplied thereto or a power down state during which the power supplied thereto is cut off, a timer that measures elapsed time starting from when the memory system transitions to the low power state, and a register in which previously measured elapsed times are stored, and in which a current measured elapsed time is stored when the memory system wakes up from the low power state. The controller controls the transitioning of the volatile memory from the retention state to the power down state, if the measured elapsed time is greater than a threshold value, which is calculated based on the previously measured elapsed times.
    Type: Grant
    Filed: February 25, 2021
    Date of Patent: May 30, 2023
    Assignee: Kioxia Corporation
    Inventors: Tasuku Kobayashi, Daisuke Uchida, Michita Fujii
  • MEMORY SYSTEM
    Publication number: 20220113907
    Abstract: A memory system includes a nonvolatile memory that stores table data and a memory controller for writing and reading data to and from the nonvolatile memory. The memory controller includes a volatile memory that can be in either a retention state during which power is supplied thereto or a power down state during which the power supplied thereto is cut off, a timer that measures elapsed time starting from when the memory system transitions to the low power state, and a register in which previously measured elapsed times are stored, and in which a current measured elapsed time is stored when the memory system wakes up from the low power state. The controller controls the transitioning of the volatile memory from the retention state to the power down state, if the measured elapsed time is greater than a threshold value, which is calculated based on the previously measured elapsed times.
    Type: Application
    Filed: February 25, 2021
    Publication date: April 14, 2022
    Inventors: Tasuku KOBAYASHI, Daisuke UCHIDA, Michita FUJII