Patents by Inventor Michitaka Yamamoto

Michitaka Yamamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11008906
    Abstract: An oil supply device includes an oil pump and an oil control valve. The oil control valve is connected to a control oil chamber of the oil pump via a control oil passage that includes an oil descent passage and an oil rise passage. One end of the oil descent passage on the control oil chamber side is disposed at a position closer to a bottom of the vehicle than the other end on the oil control valve side. The oil rise passage is disposed at a position closer to the control oil chamber side than the oil descent passage. One end of the oil rise passage on the control oil chamber side is disposed at a position closer to a top of the vehicle than the other end on the oil control valve side.
    Type: Grant
    Filed: March 7, 2018
    Date of Patent: May 18, 2021
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Shingo Okazawa, Michitaka Yamamoto
  • Patent number: 10584803
    Abstract: A solenoid valve includes: a cylindrical spool that has an annular groove in an outer surface and moves along an axial direction under a driving force generated by a current being applied to a solenoid part; a cylindrical sleeve that has a through-hole capable of communicating with the annular groove and houses the spool; and an urging member that urges the spool by an urging force acting in a direction opposite from a direction in which the driving force is generated. When no current is applied to the solenoid part, a part of the through-hole communicates with the annular groove. When a current is applied to the solenoid part, an area of communication between the through-hole and the annular groove increases as the spool moves under the driving force acting against the urging force.
    Type: Grant
    Filed: June 1, 2017
    Date of Patent: March 10, 2020
    Assignees: AISIN SEIKI KABUSHIKI KAISHA, TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Daisuke Toyama, Shinya Amano, Yoshikuni Sue, Hisashi Ono, Shingo Okazawa, Michitaka Yamamoto, Daisuke Okanishi, Noboru Takagi, Takayuki Hosogi
  • Patent number: 10344759
    Abstract: A variable displacement oil pump includes an adjustable member that is configured to shift according to changes in pressure inside a control oil chamber. The adjustable member has a long hole. A guide pin is disposed inside the long hole. The guide pin is fixed to either a housing or a cover of the variable displacement oil pump. The width of the long hole is larger at a part of the long hole farther away from a fixed end of the guide pin in its lengthwise direction than at a part thereof closer to the fixed end.
    Type: Grant
    Filed: February 13, 2017
    Date of Patent: July 9, 2019
    Assignees: TOYOTA JIDOSHA KABUSHIKI KAISHA, AISIN SEIKI KABUSHIKI KAISHA
    Inventors: Michitaka Yamamoto, Hisashi Ono, Yuki Nishida
  • Publication number: 20180266287
    Abstract: An oil supply device includes an oil pump and an oil control valve. The oil control valve is connected to a control oil chamber of the oil pump via a control oil passage that includes an oil descent passage and an oil rise passage. One end of the oil descent passage on the control oil chamber side is disposed at a position closer to a bottom of the vehicle than the other end on the oil control valve side. The oil rise passage is disposed at a position closer to the control oil chamber side than the oil descent passage. One end of the oil rise passage on the control oil chamber side is disposed at a position closer to a top of the vehicle than the other end on the oil control valve side.
    Type: Application
    Filed: March 7, 2018
    Publication date: September 20, 2018
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Shingo OKAZAWA, Michitaka YAMAMOTO
  • Publication number: 20170350527
    Abstract: A solenoid valve includes: a cylindrical spool that has an annular groove in an outer surface and moves along an axial direction under a driving force generated by a current being applied to a solenoid part; a cylindrical sleeve that has a through-hole capable of communicating with the annular groove and houses the spool; and an urging member that urges the spool by an urging force acting in a direction opposite from a direction in which the driving force is generated. When no current is applied to the solenoid part, a part of the through-hole communicates with the annular groove. When a current is applied to the solenoid part, an area of communication between the through-hole and the annular groove increases as the spool moves under the driving force acting against the urging force.
    Type: Application
    Filed: June 1, 2017
    Publication date: December 7, 2017
    Applicants: AISIN SEIKI KABUSHIKI KAISHA, TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Daisuke TOYAMA, Shinya Amano, Yoshikuni Sue, Hisashi Ono, Shingo Okazawa, Michitaka Yamamoto, Daisuke Okanishi, Noboru Takagi, Takayuki Hosogi
  • Publication number: 20170241416
    Abstract: A variable displacement oil pump includes an adjustable member that is configured to shift according to changes in pressure inside a control oil chamber. The adjustable member has a long hole. A guide pin is disposed inside the long hole. The guide pin is fixed to either a housing or a cover of the variable displacement oil pump. The width of the long hole is larger at a part of the long hole farther away from a fixed end of the guide pin in its lengthwise direction than at a part thereof closer to the fixed end.
    Type: Application
    Filed: February 13, 2017
    Publication date: August 24, 2017
    Applicants: TOYOTA JIDOSHA KABUSHIKI KAISHA, AISIN SEIKI KABUSHIKI KAISHA
    Inventors: Michitaka YAMAMOTO, Hisashi ONO, Yuki NISHIDA
  • Publication number: 20040210738
    Abstract: An on-chip multiprocessor having a chip layout for efficient multiprocessor control, wherein multiple processors and shared portions such as shared caches are symmetric with respect to a desired linear axis and a multiprocessor controller is located in the area containing said linear axis. This makes the distances between the processors and the controller equal and shorter, and also decreases differences in the distance between the controller and shared portions, thereby permitting higher speed processing of signals among these.
    Type: Application
    Filed: April 27, 2004
    Publication date: October 21, 2004
    Inventors: Takeshi Kato, Michitaka Yamamoto, Hiromichi Kaino, Teruhisa Shimizu, Masayuki Ohayashi, Hiroki Yamashita, Noboru Masuda, Tatsuya Saito
  • Patent number: 6715065
    Abstract: In an information processing apparatus which executes micro programs having branch instructions, two micro instructions are read at once, each of which instructions comprises either a field for specifying the branch target address in the following Nth (N≧2) cycle from the reading cycle of the micro instruction, or a field for determining the termination of micro program in the following Nth (N≧2) cycle, and a control field for controlling the execution in the next cycle.
    Type: Grant
    Filed: March 31, 2000
    Date of Patent: March 30, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Atsushi Ebata, Michitaka Yamamoto, Takeshi Kato
  • Patent number: 6484242
    Abstract: A cache access control system for dynamically conducting specification of dedicated and common regions and thereby always conducting optimum cache coherency control. In a processor, an L1 cache including an L1 data array and a directory is provided. A plurality of L2 caches are connected to each L1 cache. The L2 caches are connected to a main memory L3. An L2 cache history manager is supplied with L2 cache status information and an L2 cache access request from L2 caches. The L2 cache history manager judges an attribute (a dedicated region or a common region) of each line of L2. On the basis of the attribute, a cache coherency manager conducts coherency control of each L2 cache by using an invalidation type protocol or an update type protocol. The attribute is judged to be the common region, only in the case where a line shared by a plurality of L2 caches in the past is canceled once by the invalidation type protocol and then accessed again.
    Type: Grant
    Filed: March 16, 2001
    Date of Patent: November 19, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Mutsumi Hosoya, Michitaka Yamamoto
  • Publication number: 20020007440
    Abstract: A cache access control system for dynamically conducting specification of dedicated and common regions and thereby always conducting optimum cache coherency control. In a processor, an L1 cache including an L1 data array and a directory is provided. A plurality of L2 caches are connected to each L1 cache. The L2 caches are connected to a main memory L3. An L2 cache history manager is supplied with L2 cache status information and an L2 cache access request from L2 caches. The L2 cache history manager judges an attribute (a dedicated region or a common region) of each line of L2. On the basis of the attribute, a cache coherency manager conducts coherency control of each L2 cache by using an invalidation type protocol or an update type protocol. The attribute is judged to be the common region, only in the case where a line shared by a plurality of L2 caches in the past is canceled once by the invalidation type protocol and then accessed again.
    Type: Application
    Filed: March 16, 2001
    Publication date: January 17, 2002
    Applicant: Hitachi, Ltd.
    Inventors: Mutsumi Hosoya, Michitaka Yamamoto
  • Patent number: 6278296
    Abstract: In a dynamic logic circuit, a signal delay time between a low-to-high transition of an input signal and a low-to-high transition of an output signal is reduced, a through current is decreased and a time required for the precharge is reduced. In the dynamic logic circuit a P-channel type MOS transistor (PMOS) has its source electrode connected with a power supply on the side of a high voltage potential Vdd. Its gate electrode receives a clock signal Cs. A logic portion includes N-channel type MOS transistors (NMOS) connected between a drain electrode of the PMOS and a power supply on the side of a low voltage potential Vss. An NMOS is provided between an input signal connected with a NMOS closest to the Vss in the NMOSs and the Vss. A reverse signal of the clock signal Cs is connected with a gate electrode of the NMOS. An input signal is forced to change to a low level at the time of the precharge, thereby a through current is decreased and a time required for the precharge is reduced.
    Type: Grant
    Filed: August 6, 1999
    Date of Patent: August 21, 2001
    Assignee: Hitachi, Ltd.
    Inventors: Noboru Masuda, Michitaka Yamamoto
  • Patent number: 5558867
    Abstract: A recombinant Marek's disease virus produced by the mutation of a Marek's disease virus with a plasmid wherein said plasmid comprises (1) a gene fragment derived from the Us region or inverted repeat sequences adjacent to both ends of said Us region of a Marek's disease virus genome and (2) an exogenous gene expression cassette incorporated in said gene fragment, said cassette comprising an exogenous gene bound downstream of a promoter derived from an animal cell or an animal virus, a process for preparing the same, a multivalent live vaccine for birds comprising the same, and a vector for administration of a physiologically active substance to birds which comprises the same.
    Type: Grant
    Filed: July 7, 1994
    Date of Patent: September 24, 1996
    Assignee: Juridical Foundation The Chemo-Sero-Therapeutic Research Institute
    Inventors: Masashi Sakaguchi, Michitaka Yamamoto
  • Patent number: 5226132
    Abstract: Instead of translation from a space address to a segment table origin address (STO) by an ordinary instruction, translation to the STO is done by a space base register modify instruction which uses an instruction to modify the content of the space register, and the result thereof is used for the operand address calculation of the instruction to the operand data fetching. The present system eliminates the need for additionally providing for hardware of an operand fetch unit hardware for the translation from the space address to the STO, memory for storing translation pairs of the space addresses and the STO's and the table look-up of the translation pairs. Thus, degradation of performance is minimized with less hardware.
    Type: Grant
    Filed: September 27, 1989
    Date of Patent: July 6, 1993
    Assignees: Hitachi, Ltd., Hitachi Computer Engineering Co., Ltd.
    Inventors: Michitaka Yamamoto, Toshinori Kuwabara, Yoshio Oshima, Yasutaka Yamada
  • Patent number: 5171677
    Abstract: A recombinant Marek's disease virus which comprises a Marek's disease virus genom and a DNA fragment incorporated therein, said DNA fragment being constructed by incorporating a promoter derived from an animal cell or an animal virus and a structural gene coding for an exogenous protein into a gene fragment derived from a Marek's disease virus, a process for preparing the same which comprises preparing a gene fragment wherein a structural gene coding for an exogenous gene is linked to the downstream of a promoter derived from an animal cell or an animal virus, incorporating said gene fragment into a BamHI - H fragment of a gene of a Marek's disease virus type I, and incorporating said fragment into a Marek's disease virus type I genome, and a multivalent live vaccine for birds comprising the same.
    Type: Grant
    Filed: September 8, 1989
    Date of Patent: December 15, 1992
    Assignee: Juridical Foundation The Chemo-Sero-Therapeutic Research Institute
    Inventors: Masashi Sakaguchi, Hiroaki Maeda, Michitaka Yamamoto, Junichi Miyazaki