Patents by Inventor Michitaro Kanamitsu
Michitaro Kanamitsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7616516Abstract: A semiconductor device of the present invention has a memory cell array having plural CMOS static memory cells provided at intersecting portions of plural word lines and plural complementary bit lines. In the memory cell array, a switch MOSFET which is in an OFF state in a first operation mode and in an ON state in a second operation mode different from the first operation mode and first-conductivity-type and second-conductivity-type MOSFETs having a diode configuration are provided in parallel between a first source line to which sources of first-conductivity-type MOSFETs constituting first and second CMOS inverter circuits constituting the plural static memory cells are connected and a first power supply line corresponding to the first source line. A second source line to which sources of the second conductivity-type MOSFETs constituting the first and second CMOS inverter circuits are connected is connected to the second power supply line corresponding thereto.Type: GrantFiled: April 24, 2008Date of Patent: November 10, 2009Assignee: Hitachi ULSI Systems Co., LtdInventors: Masayuki Hirayama, Masami Hasegawa, Michitaro Kanamitsu, Yayoi Hayashi, Naoyuki Anan
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Patent number: 7463533Abstract: A nonvolatile memory device of the present invention performs a programming operation by accumulating a charge in certain capacitance which is provided for each programming memory cell and injecting hot electrons generated when the charge is discharged via the memory cell into a floating gate. Thus, a variation in a programming characteristic of the nonvolatile semiconductor memory device is reduced, thereby realizing high-speed programming operation.Type: GrantFiled: November 29, 2006Date of Patent: December 9, 2008Assignee: Renesas Technology Corp.Inventors: Hideaki Kurata, Naoki Kobayashi, Shunichi Saeki, Takashi Kobayashi, Takayuki Kawahara, Yoshinori Takase, Keiichi Yoshida, Michitaro Kanamitsu, Shoji Kubono, Atsushi Nozoe
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Publication number: 20080266937Abstract: A semiconductor device of the present invention has a memory cell array having plural CMOS static memory cells provided at intersecting portions of plural word lines and plural complementary bit lines. In the memory cell array, a switch MOSFET which is in an OFF state in a first operation mode and in an ON state in a second operation mode different from the first operation mode and first-conductivity-type and second-conductivity-type MOSFETs having a diode configuration are provided in parallel between a first source line to which sources of first-conductivity-type MOSFETs constituting first and second CMOS inverter circuits constituting the plural static memory cells are connected and a first power supply line corresponding to the first source line. A second source line to which sources of the second conductivity-type MOSFETs constituting the first and second CMOS inverter circuits are connected is connected to the second power supply line corresponding thereto.Type: ApplicationFiled: April 24, 2008Publication date: October 30, 2008Inventors: Masayuki HIRAYAMA, Masami Hasegawa, Michitaro Kanamitsu, Yayoi Hayashi, Naoyuki Anan
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Patent number: 7283400Abstract: A nonvolatile memory device of the present invention performs a programming operation by accumulating a charge in certain capacitance which is provided for each programming memory cell and injecting hot electrons generated when the charge is discharged via the memory cell into a floating gate. Thus, a variation in a programming characteristic of the nonvolatile semiconductor memory device is reduced, thereby realizing high-speed programming operation.Type: GrantFiled: September 19, 2005Date of Patent: October 16, 2007Assignees: Renesas Technology Corp., Hitachi Device Engineering Co., Ltd., Hitachi Ulsi Systems Co., Ltd.Inventors: Hideaki Kurata, Naoki Kobayashi, Shunichi Saeki, Takashi Kobayashi, Takayuki Kawahara, Yoshinori Takase, Keiichi Yoshida, Michitaro Kanamitsu, Shoji Kubono, Atsushi Nozoe
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Publication number: 20070076490Abstract: A nonvolatile memory device of the present invention performs a programming operation by accumulating a charge in certain capacitance which is provided for each programming memory cell and injecting hot electrons generated when the charge is discharged via the memory cell into a floating gate. Thus, a variation in a programming characteristic of the nonvolatile semiconductor memory device is reduced, thereby realizing high-speed programming operation.Type: ApplicationFiled: November 29, 2006Publication date: April 5, 2007Inventors: Hideaki Kurata, Naoki Kobayashi, Shunichi Saeki, Takashi Kobayashi, Takayuki Kawahara, Yoshinori Takase, Keiichi Yoshida, Michitaro Kanamitsu, Shoji Kubono, Atsushi Nozoe
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Patent number: 7095657Abstract: A nonvolatile semiconductor memory device capable of realizing optimized erasing operation in a memory array configuration in which a plurality of pages correspond to and are connected to each of a plurality of word lines and higher speed of the erasing operation. In a flash memory, the erasing operation is performed by an erasing method of erasing a plurality of pages arbitrarily selected in a lump. In a two-page erasing mode, page erasure, page pre-erasure verification, page rewriting process, page pre-rewriting verification, and page upper end determining process are performed in order.Type: GrantFiled: September 14, 2005Date of Patent: August 22, 2006Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Inc.Inventors: Yoshinori Takase, Hideaki Kurata, Keiichi Yoshida, Ken Matsubara, Michitaro Kanamitsu, Shinji Yuasa
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Patent number: 7072225Abstract: There is provided a method of programming a non-volatile memory which can solve the problem of the data write system of the existing flash memory that a load capacitance of bit lines becomes large, the time required by the bit lines to reach the predetermined potential becomes longer, thereby the time required for data write operation becomes longer and power consumption also becomes large because the more the memory capacitance of memory array increases, the longer the length of bit lines becomes and the more the number of bit lines increases.Type: GrantFiled: June 29, 2005Date of Patent: July 4, 2006Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Yoshinori Takase, Shoji Kubono, Michitaro Kanamitsu, Atsushi Nozoe, Keiichi Yoshida, Hideaki Kurata
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Patent number: 7002848Abstract: This is a nonvolatile semiconductor memory device capable of raising the speed of write operation of Y access circuits in a 1×sense latch circuit+2×SRAM configuration. In a multi-value flash memory, in a mode of writing from the lower voltage side, writing and erratic determination are performed after data are transferred from SRAMs to a sense latch circuit for “10” and “00” distributions; after the data transfer for “01” distribution, writing is done; after the data transfer for “11” distribution word disturb determination is done; and simplified upper limit determination is done in this sequence.Type: GrantFiled: February 28, 2002Date of Patent: February 21, 2006Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Yoshinori Takase, Hideaki Kurata, Keiichi Yoshida, Michitaro Kanamitsu
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Patent number: 6999348Abstract: A nonvolatile semiconductor storage unit can prevent erratic sense operations in a sense latch circuit by adopting a single-end sensing system capable of reducing an area (decreasing the number of elements). There is provided a flash memory chip using the single-end sensing system and an NMOS gate sensing system together. In the single-end sensing system, the sense latch circuit is connected to one end of a global bit line to detect data on the global bit line corresponding to a threshold voltage for a memory cell. The NMOS gate sensing system uses an NMOSFET to receive data on the global bit line at a gate and drive a node for the sense latch circuit. The NMOSFET senses a sense voltage. The sense latch circuit is activated with a sufficient signal quantity ensured. An output voltage from a threshold voltage applying power supply precharges the global bit line. In this manner, it is possible to always keep a constant difference between a precharge voltage and a threshold voltage for the NMOSFET.Type: GrantFiled: February 28, 2002Date of Patent: February 14, 2006Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Michitaro Kanamitsu, Yoshinori Takase, Shoji Kubono
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Patent number: 6992936Abstract: Externally supplied program data is latched into data latch circuits DLL and DLR. A judgment is made as to whether or not the latched program data corresponds to any threshold value of multi-levels every time each of plural programing operations is carried out. The program control information corresponding to the judgment result is latched into a sense latch circuit SL. Based upon the latched program control information, the programing operation for setting threshold voltages having multi-levels to a memory cell is carried out in a stepwise manner. Even when the programing operation is ended, the externally supplied program data is left in the data latch circuit. Even when the programing operation of the memory cell is retried due to the overprograming condition, the program data is no longer required to be again received from the external device.Type: GrantFiled: February 12, 2004Date of Patent: January 31, 2006Assignees: Renesas Technology Corp., Hitachi Ulsi Systems Co., Ltd.Inventors: Tetsuya Tsujikawa, Atsushi Nozoe, Michitaro Kanamitsu, Shoji Kubono, Eiji Yamamoto, Ken Matsubara
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Publication number: 20060013032Abstract: A nonvolatile memory device of the present invention performs a programming operation by accumulating a charge in certain capacitance which is provided for each programming memory cell and injecting hot electrons generated when the charge is discharged via the memory cell into a floating gate. Thus, a variation in a programming characteristic of the nonvolatile semiconductor memory device is reduced, thereby realizing high-speed programming operation.Type: ApplicationFiled: September 19, 2005Publication date: January 19, 2006Inventors: Hideaki Kurata, Naoki Kobayashi, Shunichi Saeki, Takashi Kobayashi, Takayuki Kawahara, Yoshinori Takase, Keiichi Yoshida, Michitaro Kanamitsu, Shoji Kubono, Atsushi Nozoe
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Publication number: 20060007737Abstract: A nonvolatile semiconductor memory device capable of realizing optimized erasing operation in a memory array configuration in which a plurality of pages correspond to and are connected to each of a plurality of word lines and higher speed of the erasing operation. In a flash memory, the erasing operation is performed by an erasing method of erasing a plurality of pages arbitrarily selected in a lump. In a two-page erasing mode, page erasure, page pre-erasure verification, page rewriting process, page pre-rewriting verification, and page upper end determining process are performed in order.Type: ApplicationFiled: September 14, 2005Publication date: January 12, 2006Inventors: Yoshinori Takase, Hideaki Kurata, Keiichi Yoshida, Ken Matsubara, Michitaro Kanamitsu, Shinji Yuasa
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Publication number: 20050237803Abstract: There is provided a method of programming a non-volatile memory which can solve the problem of the data write system of the existing flash memory that a load capacitance of bit lines becomes large, the time required by the bit lines to reach the predetermined potential becomes longer, thereby the time required for data write operation becomes longer and power consumption also becomes large because the more the memory capacitance of memory array increases, the longer the length of bit lines becomes and the more the number of bit lines increases.Type: ApplicationFiled: June 29, 2005Publication date: October 27, 2005Inventors: Yoshinori Takase, Shoji Kubono, Michitaro Kanamitsu, Atsushi Nozoe, Keiichi Yoshida, Hideaki Kurata
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Patent number: 6958940Abstract: A nonvolatile semiconductor memory device capable of realizing optimized erasing operation in a memory array configuration in which a plurality of pages correspond to and are connected to each of a plurality of word lines and higher speed of the erasing operation. In a flash memory, the erasing operation is performed by an erasing method of erasing a plurality of pages arbitrarily selected in a lump. In a two-page erasing mode, page erasure, page pre-erasure verification, page rewriting process, page pre-rewriting verification, and page upper end determining process are performed in order.Type: GrantFiled: February 28, 2002Date of Patent: October 25, 2005Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Yoshinori Takase, Hideaki Kurata, Keiichi Yoshida, Ken Matsubara, Michitaro Kanamitsu, Shinji Yuasa
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Patent number: 6930924Abstract: There is provided a method of programming a non-volatile memory which can solve the problem of the data write system of the existing flash memory that a load capacitance of bit lines becomes large, the time required by the bit lines to reach the predetermined potential becomes longer, thereby the time required for data write operation becomes longer and power consumption also becomes large because the more the memory capacitance of memory array increases, the longer the length of bit lines becomes and the more the number of bit lines increases.Type: GrantFiled: April 2, 2003Date of Patent: August 16, 2005Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Yoshinori Takase, Shoji Kubono, Michitaro Kanamitsu, Atsushi Nozoe, Keiichi Yoshida, Hideaki Kurata
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Publication number: 20050105373Abstract: This is a nonvolatile semiconductor memory device capable of raising the speed of write operation of Y access circuits in a 1×sense latch circuit+2×SRAM configuration. In a multi-value flash memory, in a mode of writing from the lower voltage side, writing and erratic determination are performed after data are transferred from SRAMs to a sense latch circuit for “10” and “00” distributions; after the data transfer for “01” distribution, writing is done; after the data transfer for “11” distribution word disturb determination is done; and simplified upper limit determination is done in this sequence.Type: ApplicationFiled: February 28, 2002Publication date: May 19, 2005Inventors: Yoshinori Takase, Hideaki Kurata, Keiichi Yoshida, Michitaro Kanamitsu
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Publication number: 20050095769Abstract: A nonvolatile semiconductor memory device capable of realizing optimized erasing operation in a memory array configuration in which a plurality of pages correspond to and are connected to each of a plurality of word lines and higher speed of the erasing operation. In a flash memory, the erasing operation is performed by an erasing method of erasing a plurality of pages arbitrarily selected in a lump. In a two-page erasing mode, page erasure, page pre-erasure verification, page rewriting process, page pre-rewriting verification, and page upper end determining process are performed in order.Type: ApplicationFiled: February 28, 2002Publication date: May 5, 2005Inventors: Yoshinori Takase, Hideaki Kurata, Keiichi Yoshida, Ken Matsubara, Michitaro Kanamitsu, Shinji Yuasa
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Publication number: 20050047212Abstract: A nonvolatile semiconductor storage unit can prevent erratic sense operations in a sense latch circuit by adopting a single-end sensing system capable of reducing an area (decreasing the number of elements). There is provided a flash memory chip using the single-end sensing system and an NMOS gate sensing system together. In the single-end sensing system, the sense latch circuit is connected to one end of a global bit line to detect data on the global bit line corresponding to a threshold voltage for a memory cell. The NMOS gate sensing system uses an NMOSFET to receive data on the global bit line at a gate and drive a node for the sense latch circuit. The NMOSFET senses a sense voltage. The sense latch circuit is activated with a sufficient signal quantity ensured. An output voltage from a threshold voltage applying power supply precharges the global bit line. In this manner, it is possible to always keep a constant difference between a precharge voltage and a threshold voltage for the NMOSFET.Type: ApplicationFiled: February 28, 2002Publication date: March 3, 2005Inventors: Michitaro Kanamitsu, Yoshinori Takase, Shoji Kubono
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Publication number: 20050024948Abstract: The present invention provides a semiconductor device such as a multi-valued flash memory or the like, which is capable of shortening a processing time required to set write control information to a sense latch. The semiconductor device is capable of electrically writing multi-value information therein. Bit lines are connected to the right and left input/output terminals of a sense latch, and data latches are connected to the respective bit lines. A decoder is provided which decodes write data supplied from outside to thereby generate write control information. The write control information is latched in each of the sense latch and data latches, and the latched control information is set as information indicative of go/no-go of the application of a write voltage, which corresponds to each value in a multivalue.Type: ApplicationFiled: August 30, 2004Publication date: February 3, 2005Inventors: Michitaro Kanamitsu, Yoshinori Takase
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Patent number: 6829178Abstract: A counter circuit for counting the number of fails generated during the write and erase processes executed in the predetermined unit such as a sector and a comparison circuit for judging whether the value counted with the counter circuit has exceeded or not the preset allowable value for the number of fails are provided. Accordingly, when the counted value of the counter circuit has exceeded the allowable value set to a register, the write process or erase process is not performed even when a write or erase command is inputted from an external circuit. Thereby, the required test time can be shortened for the electrically programmable and erasable nonvolatile semiconductor memory device such as a flash memory.Type: GrantFiled: October 15, 2002Date of Patent: December 7, 2004Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Hiyori Koyama, Kazuyoshi Oshima, Akihiko Hoshida, Kiichi Manita, Michitaro Kanamitsu, Shinji Udo, Kazue Kikuchi, Kazuaki Ujiie, Masahiro Sakai