Abstract: A non-volatile semiconductor memory device is divided into a first region I and a second region II. In the first region, an n+ layer is formed to be enlarged from a source region 3 to beneath a floating gate 6. A p+ layer is formed in a channel region 4. The p+ layer serves to prevent a short channel effect from occurring during read of data. A capacitance coupling ratio C1/C2 between a control gate and the floating gate is preferably 0.8 or larger. In this configuration, the non-volatile semiconductor can write, erase and read data at a high speed using a low voltage.