Patents by Inventor Michitomo Iiyama

Michitomo Iiyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120063161
    Abstract: A light source device includes a single optical waveguide, a plurality of optical sub-assemblies, and an assembly holder. The optical waveguide includes a core area extending along a predetermined axis, a cladding area covering a periphery of the core area, and a first end face extending along a plane intersecting the predetermined axis. The assembly holder has an inner surface supporting the optical sub-assemblies so that the optical sub-assemblies are respectively arranged on a plurality of reference lines and optically coupled to the first end face of the optical waveguide. Each optical sub-assembly includes a semiconductor light-emitting element having a light-emitting surface optically coupled to the first end face of the optical waveguide, and a support member on which the semiconductor light-emitting element is mounted. The reference lines extend in different directions from one point on a predetermined axis of the core area to the cladding area.
    Type: Application
    Filed: September 13, 2011
    Publication date: March 15, 2012
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Hiromi NAKANISHI, Michitomo IIYAMA
  • Patent number: 6613463
    Abstract: A superconducting laminated oxide substrate, which comprises a laminate a layer of a superconducting oxide crystal substrate made of a superconducting oxide single crystal or a superconducting oxide polycrystal and a layer of a reinforcing crystal substrate, prevents cracks from occurring in the superconducting oxide crystal substrate due to the heat treatment conducted for the purpose of forming an insulation film or a conductor film, and provides easy connectivity between electrodes and wiring formed on substrates located at upper and lower positions.
    Type: Grant
    Filed: September 1, 2000
    Date of Patent: September 2, 2003
    Assignee: International Superconductivity Technology Center
    Inventors: Teruo Izumi, Satoshi Koyama, Yuh Shiohara, Shoji Tanaka, Masahiro Egami, Youichi Enomoto, Hideo Suzuki, Michitomo Iiyama
  • Patent number: 6524643
    Abstract: The invention provides a method for preparing a layered structure comprising a lower thin film composed of an oxide superconductor and an upper thin film composed of a material different from the oxide superconductor on a substrate. The lower thin film is deposited by a molecular beam deposition process and the upper thin film is deposited by a process having a deposition rate faster than that of the molecular beam deposition process.
    Type: Grant
    Filed: August 8, 1997
    Date of Patent: February 25, 2003
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takao Nakamura, Michitomo Iiyama
  • Patent number: 5977479
    Abstract: There is disclosed a structure for coupling between a low temperature circuitry cooled by a cooling system and a room temperature circuitry wherein the structure contains a device for electric connection and a second cooling system specifically for cooling of the electric connection.
    Type: Grant
    Filed: October 24, 1994
    Date of Patent: November 2, 1999
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Hitoki Tokuda, Michitomo Iiyama
  • Patent number: 5861361
    Abstract: A FET type superconducting device comprises a thin superconducting channel, a superconducting source region and a superconducting drain region formed of an oxide superconductor over a principal surface of the substrate, and a gate electrode on a gate insulator disposed on the superconducting channel for controlling the superconducting current flowing through the superconducting channel by a signal voltage applied to the gate electrode. The superconducting channel is formed of(Pr.sub.w Y.sub.1-w)Ba.sub.2 Cu.sub.3 O.sub.7-z (0<w<1, 0<z<1) oxide superconductororY.sub.1 Ba.sub.2 Cu.sub.3-v CO.sub.V O.sub.7-u (0<v<3, 0<u<1) oxide superconductor.These oxide superconductors have smaller carrier densities than the conventional oxide superconductor so that the superconducting channel has a larger thickness than the one funned of the conventional oxide superconductor.
    Type: Grant
    Filed: April 17, 1996
    Date of Patent: January 19, 1999
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takao Nakamura, Michitomo Iiyama
  • Patent number: 5856275
    Abstract: Patterned superconducting wiring lines each having a portion of a thin film of an oxide superconductor deposited on a flat substrate, the portion having a predetermined crystal orientation (a-axis or c-axis orientation) with respect to a flat surface of the substrate, remaining portions of the thin film of the oxide superconductor having a different crystal orientation (c-axis or a-axis orientation) from the portion and/or having an insulation zones. Both of the portion and the remaining portions have a substantially identical thickness so that the thin film has a substantially flat planar surface.
    Type: Grant
    Filed: November 1, 1991
    Date of Patent: January 5, 1999
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Hiroshi Inada, Takao Nakamura, Michitomo Iiyama
  • Patent number: 5854493
    Abstract: A superconducting device has a substrate, and a superconducting channel provided by an oxide superconductor thin film formed to have an angle with respect to a deposition surface of the substrate. A superconductor source electrode region and a superconductor drain electrode region are formed at opposite ends of the superconducting channel, so that a superconducting current can flow through the superconducting channel between the superconductor source electrode region and the superconductor drain electrode region. A gate electrode region is formed of a oxide superconductor thin film which is deposited in parallel to the deposition surface of the substrate and which has an end portion which abuts with an insulating layer which separates the end portion and the superconducting channel so as to control superconducting current flow through the superconducting channel.
    Type: Grant
    Filed: April 14, 1997
    Date of Patent: December 29, 1998
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takao Nakamura, Hiroshi Inada, Michitomo Iiyama
  • Patent number: 5840204
    Abstract: A method for patterning an oxide superconductor thin film, comprising a step of forming a SiO.sub.2 layer on the oxide superconductor thin film, patterning the SiO.sub.2 layer so as to form the same pattern as that of the oxide superconductor thin film which will be patterned, etching the oxide superconductor thin film by using the patterned SiO.sub.2 layer as a mask, and removing the SiO.sub.2 layer by using a weak HF solution, a buffer solution including HF or a mixture including HF.
    Type: Grant
    Filed: April 5, 1995
    Date of Patent: November 24, 1998
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Hiroshi Inada, So Tanaka, Michitomo Iiyama
  • Patent number: 5817531
    Abstract: A superconducting device comprises a substrate having a principal surface, a non-superconducting oxide layer having a similar crystal structure to that of an oxide superconductor formed on the principal surface, which can compensates the lattice mismatch between the substrate and the oxide superconductor, a superconducting source region and a superconducting drain region formed of c-axis oriented oxide superconductor thin films on the non-superconducting oxide layer, and an insulating region formed of a doped oxide superconductor on the non-superconducting oxide layer separating the superconducting source region and the superconducting drain region between them. On the insulating region an extremely thin superconducting channel formed of a c-axis oriented oxide superconductor thin film is arranged.
    Type: Grant
    Filed: October 7, 1996
    Date of Patent: October 6, 1998
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takao Nakamura, Michitomo Iiyama
  • Patent number: 5811375
    Abstract: A superconducting multilayer interconnection comprises a substrate having a principal surface, a first superconducting current path of a c-axis orientated oxide superconductor thin film formed on the principal surface of the substrate, an insulating layer on the first superconducting current path, and a second superconducting current path of a c-axis orientated oxide superconductor thin film formed on the insulating layer so that the first and second superconducting current paths are insulated by the insulating layer. The superconducting multilayer interconnection further comprises a superconducting interconnect current path of an a-axis orientated oxide superconductor thin film, through which the first and second superconducting current paths are electrically connected each other.
    Type: Grant
    Filed: June 30, 1995
    Date of Patent: September 22, 1998
    Assignee: Sumitomo Electric Industries Ltd.
    Inventors: Takao Nakamura, Hiroshi Inada, Michitomo Iiyama
  • Patent number: 5789346
    Abstract: Method for manufacturing a superconducting device including forming on a surface of a substrate a non-superconducting oxide layer, a first oxide superconductor thin film, etching the first oxide superconductor thin film so as to form a concave portion, implanting ions to the first oxide superconductor thin film at the bottom of the concave portion so as to form an insulating region such that the first oxide superconductor thin film is divided into two superconducting regions by the insulating region, and forming a second oxide superconductor thin film on the insulating region and the two superconducting regions, which is continuous to the two superconducting regions.
    Type: Grant
    Filed: May 20, 1996
    Date of Patent: August 4, 1998
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takao Nakamura, Hiroshi Inada, Michitomo Iiyama
  • Patent number: 5773843
    Abstract: A metal electrode disposed on a surface of an oxide superconductor and forming electric contact with the oxide superconductor wherein at least a portion of the metal electrode is in contact with a side surface of the oxide superconductor which is perpendicular to the surface on which the metal electrode is disposed.
    Type: Grant
    Filed: February 20, 1996
    Date of Patent: June 30, 1998
    Assignee: Sumitomo Electric Industries, Inc.
    Inventors: Takao Nakamura, Michitomo Iiyama
  • Patent number: 5739084
    Abstract: A method for fabricating a superconducting device with a substrate, a first oxide superconductor thin film, a barrier layer, a diffusion layer, and a second oxide superconductor thin film. The first oxide superconductor thin film with a very thin thickness is formed on the principal surface of the substrate. The barrier layer and the diffusion source layer are formed on a portion of the first oxide superconductor thin film. The second oxide superconductor thin film is grown on an exposed surface of the first oxide superconductor thin film until the barrier and diffusion source layers are embedded in the second oxide superconductor thin film, so that a material of the diffusion source layer is diffused into the second oxide superconductor thin film.
    Type: Grant
    Filed: January 2, 1997
    Date of Patent: April 14, 1998
    Assignee: Sumitomo Electric Industries Ltd.
    Inventors: Takao Nakamura, Hiroshi Inada, Michitomo Iiyama
  • Patent number: 5721196
    Abstract: A Josephson junction device comprises a single crystalline substrate including a principal surface, an oxide layer formed on the principal surface of the substrate having a step on its surface and an oxide superconductor thin film formed on the surface of the oxide layer. The oxide superconductor thin film includes a first and a second portions respectively positioned above and below the step of the oxide layer, which are constituted of single crystals of the oxide superconductor, and a step-edge junction made up of a grain boundary on the step of the oxide layer, which constitutes a weak link of the Josephson junction.
    Type: Grant
    Filed: August 16, 1996
    Date of Patent: February 24, 1998
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takao Nakamura, Michitomo Iiyama
  • Patent number: 5717222
    Abstract: A superconducting device includes a substrate, a projecting insulating region formed in a principal surface of the substrate, and a first thin film portion of an oxide superconductor formed on the projecting insulating region. Second and third thin film portions of an oxide superconductor are positioned at opposite sides of the projecting insulating region to be continuous to the first thin film portion, respectively, so that a superconducting current can flow through the first thin film portion between the second thin film portion and the third thin film portion. The second thin film portion and the third thin film portion has a thickness larger than that of the first thin film portion. The projecting insulating region is formed of an oxide which is composed of the same constituent elements of the oxide superconductor but which has the oxygen content smaller than that of said oxide superconductor.
    Type: Grant
    Filed: May 23, 1996
    Date of Patent: February 10, 1998
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takao Nakamura, Hiroshi Inada, Michitomo Iiyama
  • Patent number: 5714767
    Abstract: For manufacturing a superconducting device, a compound layer which is composed of the same constituent elements of an oxide superconductor is formed on a surface of the substrate, and a gate electrode is formed on a portion of the compound layer. Portions of the compound layer at both sides of die gate electrode are etched using die gate electrode as a mask, so that a shallow step is formed on an upper surface of the compound layer and side surfaces of the step exposed. After that electric power is applied to the gate electrode to heat the gate electrode so as to carry out a heat-treatment on the portion of die compound layer under the gate electrode locally, so that a gate insulator formed directly under the the gate electrode and a superconducting channel which is constituted an extremely thin superconducting region composed of the oxide superconductor and formed under die gate insulator are produced in a self alignment to die gate electrode.
    Type: Grant
    Filed: November 1, 1995
    Date of Patent: February 3, 1998
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takao Nakamura, Hiroshi Inada, Michitomo Iiyama
  • Patent number: 5683968
    Abstract: A superconducting device or a super-FET has a pair of superconducting electrode regions (20b, 20c) consisting of a thin film (20) oxide superconductor being deposited on a substrate (5) and a weak/ink region (20a), the superconducting electrode regions (20b, 20c) being positioned at opposite sides of the weak link region (20a), these superconducting electrode regions (20b, 20c) and the weak link region (20a) being formed on a common plane surface of the substrate (5). The weak link region (20a) is produced by local diffusion of constituent element(s) of the substrate (5) and/or a gate electrode insulating layer (16) into the thin film (20) of the oxide superconductor in such a manner that a substantial wall thickness of the thin film (20) of the oxide superconductor is reduced at the weak link region (20a) so as to leave a weak link or superconducting channel (10) in the thin film (20) of oxide superconductor over a non-superconducting region (50) which is produced by the diffusion.
    Type: Grant
    Filed: August 31, 1995
    Date of Patent: November 4, 1997
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takao Nakamura, Hiroshi Inada, Michitomo Iiyama
  • Patent number: 5674813
    Abstract: The invention provides a method for preparing a layered structure made up of a plurality of thin films composed of different compositions, in which the method involves using a reactive co-evaporation technique to deposit a first thin film on a substrate using a first set of evaporation sources, and then depositing another thin film of a different composition on the first thin film, using a second set of evaporation sources that has no evaporation sources common with the first set of evaporation sources. In the method, the first thin film is deposited in a first deposition sub-chamber and the second thin film is deposited in a second deposition subchamber, both of which are part of a single vacuum chamber.
    Type: Grant
    Filed: July 15, 1996
    Date of Patent: October 7, 1997
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takao Nakamura, Michitomo Iiyama
  • Patent number: 5672569
    Abstract: A superconducting circuit having patterned superconducting wiring lines. Each wiring line consists of at least one portion (2') of the thin film (2) of an oxide superconductor deposited on a substrate (1). The portion (2') has a predetermined crystal orientation and the remaining portions (2") have a different crystal orientation or changed to non-superconductor. The superconducting circuit has a planar surface.In variations, two different wiring lines (21, 22) each having a different crystal orientation are produced at different portions of a thin film of oxide superconductor, so that superconducting current flow separately through two different portions in a common thin film.
    Type: Grant
    Filed: March 8, 1995
    Date of Patent: September 30, 1997
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takao Nakamura, Hiroshi Inada, Michitomo Iiyama
  • Patent number: 5637555
    Abstract: A method for manufacturing a three-terminal superconducting device is disclosed. A superconducting channel constituted in an oxide superconductor thin film is deposited on a deposition surface of a substrate. A gate electrode for the device is formed through a gate insulator layer on the superconducting channel of the device. The steps of forming the gate electrode include forming a thin film that stands upright with respect to the insulator layer for the gate.
    Type: Grant
    Filed: August 23, 1995
    Date of Patent: June 10, 1997
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takao Nakamura, Hiroshi Inada, Michitomo Iiyama