Abstract: The method for producing an SiC epitaxial wafer according to the present invention includes: a step of vacuum baking a coated carbon-based material member at a degree of vacuum of 2.0×10?3 Pa or less in a dedicated vacuum baking furnace; a step of installing the coated carbon-based material member in an epitaxial wafer manufacturing apparatus; and a step of placing an SiC substrate in the epitaxial wafer manufacturing apparatus and epitaxially growing an SiC epitaxial film on the SiC substrate.

Abstract: A method of manufacturing a SiC epitaxial wafer wherein a SiC epitaxial layer is provided on a SiC single crystal substrate having an off angle. The method includes determining a ratio of basal plane dislocations (BPD) which cause stacking faults in a SiC epitaxial film of a prescribed thickness, to basal plane dislocations which are present on a growth surface of the SiC single crystal substrate, determining an upper limit of surface density of basal plane dislocations, preparing a SiC single crystal substrate which has surface density equal to or less than the above upper limit, and forming a SiC epitaxial film on the SiC single crystal substrate under the same conditions as the growth conditions of the epitaxial film used in the step of determining the ratio.

Abstract: A SiC epitaxial wafer obtained by forming a SiC epitaxial layer on a 4H—SiC single-crystal substrate that is tilted at an off-angle of 0.4° to 5°, wherein linear density of step bunchings, which are connected to shallow pits which are due to screw dislocation in the SiC epitaxial wafer, is 5 mm?1 or less.

Abstract: Provided is a silicon carbide epitaxial wafer, the entire surface of which is free of step bunching. Also provided is a method for manufacturing said silicon carbide epitaxial wafer. The provided method for manufacturing a silicon carbide semiconductor device includes: a step wherein a 4H—SiC single-crystal substrate having an off-axis angle of 5° or less is polished until the lattice disorder layer on the surface of the substrate is 3 nm or less; a step wherein, in a hydrogen atmosphere, the polished substrate is brought to a temperature between 1400° C. and 1600° C. and the surface of the substrate is cleaned; a step wherein silicon carbide is epitaxially grown on the surface of the cleaned substrate as the amounts of SiH4 gas and C3H8 gas considered necessary for epitaxially growing silicon carbide are supplied simultaneously at a carbon-to-silicon concentration ratio between 0.7 and 1.

Abstract: Provided are a SiC epitaxial wafer in which the surface density of stacking faults is reduced, and a manufacturing method thereof. The method for manufacturing such a SiC epitaxial wafer comprises a step of determining a ratio of basal plane dislocations (BPD), which causes stacking faults in a SiC epitaxial film of a prescribed thickness which is formed on a SiC single crystal substrate having an off angle, to basal plane dislocations which are present on a growth surface of the SiC single crystal substrate, a step of determining an upper limit of surface density of basal plane dislocations on the growth surface of a SiC single crystal substrate used based on the above ratio, and a step of preparing a SiC single crystal substrate which has surface density equal to or less than the above upper limit, and forming a SiC epitaxial film on the SiC single crystal substrate under the same conditions as the growth conditions of the epitaxial film used in the step of determining the ratio.

Abstract: An epitaxial SiC single crystal substrate including a SiC single crystal wafer whose main surface is a c-plane or a surface that inclines a c-plane with an angle of inclination that is more than 0 degree but less than 10 degrees, and SiC epitaxial film that is formed on the main surface of the SiC single crystal wafer, wherein the dislocation array density of threading edge dislocation arrays that are formed in the SiC epitaxial film is 10 arrays/cm2 or less.

Abstract: An epitaxial SiC single crystal substrate including a SiC single crystal wafer whose main surface is a c-plane or a surface that inclines a c-plane with an angle of inclination that is more than 0 degree but less than 10 degrees, and SiC epitaxial film that is formed on the main surface of the SiC single crystal wafer, wherein the dislocation array density of threading edge dislocation arrays that are formed in the SiC epitaxial film is 10 arrays/cm2 or less.

Abstract: According to the present invention, there is provided an SiC epitaxial wafer which reduces triangular defects and stacking faults, which is highly uniform in carrier concentration and film thickness, and which is free of step bunching, and its method of manufacture. The SiC epitaxial wafer of the present invention is an SiC epitaxial wafer in which an SiC epitaxial layer is formed on a 4H—SiC single crystal substrate that is tilted at an off angle of 0.4°-5°, wherein the density of triangular-shaped defects of said SiC epitaxial layer is 1 defect/cm2 or less.

Abstract: An epitaxial SiC single crystal substrate including a SiC single crystal wafer whose main surface is a c-plane or a surface that inclines a c-plane with an angle of inclination that is more than 0 degree but less than 10 degrees, and SiC epitaxial film that is formed on the main surface of the SiC single crystal wafer, wherein the dislocation array density of threading edge dislocation arrays that are formed in the SiC epitaxial film is 10 arrays/cm2 or less.

Abstract: Provided is a silicon carbide epitaxial wafer, the entire surface of which is free of step bunching. Also provided is a method for manufacturing said silicon carbide epitaxial wafer. The provided method for manufacturing a silicon carbide semiconductor device includes: a step wherein a 4H—SiC single-crystal substrate having an off-axis angle of 5° or less is polished until the lattice disorder layer on the surface of the substrate is 3 nm or less; a step wherein, in a hydrogen atmosphere, the polished substrate is brought to a temperature between 1400° C. and 1600° C. and the surface of the substrate is cleaned; a step wherein silicon carbide is epitaxially grown on the surface of the cleaned substrate as the amounts of SiH4 gas and C3H8 gas considered necessary for epitaxially growing silicon carbide are supplied simultaneously at a carbon-to-silicon concentration ratio between 0.7 and 1.

Abstract: An epitaxial SiC single crystal substrate including a SiC single crystal wafer whose main surface is a c-plane or a surface that inclines a c-plane with an angle of inclination that is more than 0 degree but less than 10 degrees, and SiC epitaxial film that is formed on the main surface of the SiC single crystal wafer, wherein the dislocation array density of threading edge dislocation arrays that are formed in the SiC epitaxial film is 10 arrays/cm2 or less.

Abstract: A pn-heterojunction compound semiconductor light-emitting device includes a crystalline substrate 101, a lower cladding layer 102 formed on a surface of the crystalline substrate and composed of an n-type Group III-V compound semiconductor, a light-emitting layer 103 formed on a surface of the lower cladding layer and composed of an n-type Group III-V compound semiconductor, an upper cladding layer 105 formed on a surface of the light-emitting layer and composed of p-type boron phosphide, an n-type electrode 106 attached to the lower cladding layer and a p-type electrode 107 attached to the upper cladding layer. The lower and upper cladding layers are opposed to each other and sandwich the light-emitting layer to form, in cooperation with the light-emitting layer, a light-emitting portion of a pn-heterojunction structure. The light-emitting device has an intermediate layer 104 composed of an n-type boron-containing Group III-V compound between the light-emitting layer and the upper cladding layer.

Abstract: In a p-n junction-type compound semiconductor light-emitting diode provided on a crystal substrate with at least an n-type active layer formed of a Group m nitride semiconductor as a light emitting layer, and with a Group m nitride semiconductor layer containing a p-type impurity on the n-type active layer, the diode has a boron phosphide-based Group III-V compound semiconductor layer possessing a band gap exceeding that of the Group m nitride semiconductor forming the n-type active layer at room temperature and exhibiting a p-type electroconductivity in an undoped state deposited on the p-type impurity-containing Group III nitride semiconductor layer, and has an ohmic positive electrode joined to a surface of the boron phosphide-based Group III-V compound semiconductor layer.

Abstract: A pn-heterojunction compound semiconductor light-emitting device includes a crystalline substrate 101, a lower cladding layer 102 formed on a surface of the crystalline substrate and composed of an n-type Group III-V compound semiconductor, a light-emitting layer 103 formed on a surface of the lower cladding layer and composed of an n-type Group III-V compound semiconductor, an upper cladding layer 105 formed on a surface of the light-emitting layer and composed of p-type boron phosphide, an n-type electrode 106 attached to the lower cladding layer and a p-type electrode 107 attached to the upper cladding layer. The lower and upper cladding layers are opposed to each other and sandwich the light-emitting layer to form, in cooperation with the light-emitting layer, a light-emitting portion of a pn-heterojunction structure. The light-emitting device has an intermediate layer 104 composed of an n-type boron-containing Group III-V compound between the light-emitting layer and the upper cladding layer.