Abstract: Techniques are provided for generating a hash value for searching for substrings in a data stream without reading more than one element (e.g. one byte) at a time. According to one technique, a before a next element is added to an old hash value, the old hash value is circularly shifted one or more bits. The first original element is shifted a number of bits and XOR'ed against the old hash value. The next element is added to the old hash value. In one embodiment, an entry value is retrieved for each element from an index table and the XOR and shift operations are performed on the entry values. According to another technique, each Linear Feedback Shift Register (LFSR) of a plurality of LFSRs read in one element at a time beginning at different offsets. Each LFSR uses the same state machine. The result of reading a number of elements into an LFSR is used as the hash value.

Abstract: Techniques are provided for generating a hash value for searching for substrings in a data stream without reading more than one element (e.g. one byte) at a time. According to one technique, a before a next element is added to an old hash value, the old hash value is circularly shifted one or more bits. The first original element is shifted a number of bits and XOR'ed against the old hash value. The next element is added to the old hash value. In one embodiment, an entry value is retrieved for each element from an index table and the XOR and shift operations are performed on the entry values. According to another technique, each Linear Feedback Shift Register (LFSR) of a plurality of LFSRs read in one element at a time beginning at different offsets. Each LFSR uses the same state machine. The result of reading a number of elements into an LFSR is used as the hash value.

Abstract: A system and method for selecting a best transmit antenna for a transceiver using antenna diversity that caches the identity of the best transmit antenna for each remote node from which a message has been received. The best transmit antenna is then selected for each message sent to a remote node having a cache entry.

Abstract: The development port or Debug port of a microprocessor on an intelligent daughterboard is used for downloading code or configuration information from a motherboard for use in boot-up. In various aspects, the code or configuration information can include information used for configuring a port, other than the development port, and/or for configuring a memory controller, such as for a daughterboard DRAM. Use of the Debug port makes it possible to reduce or eliminate the need for storing boot-up code or configuration information on a daughterboard ROM, or other non-volatile memory, thus reducing cost and space requirements, power consumption and the like.

Abstract: A method and apparatus are described for transmitting data in a network between first and second single-line digital subscriber line (SDSL) modems using a standard high data rate digital subscriber line (HDSL) frame format. The frame format includes at least one field in each data payload block, e.g., the F/Z bit field, for implementing a feature relating to one of the T1 and E1 transmission protocols. According to the invention, the at least one field is employed for transmission of selected payload data.

Abstract: A method and apparatus for implementing host management of an intelligent daughtercard utilizes a high-speed serial link and a defined plurality of serial protocol commands to provide high bandwidth control path for management of daughtercard memory and application specific initialization and/or configuration changes.

Abstract: Methods and apparatus for transmitting and receiving data using framing circuitry designed to generate data frames of a first duration at a first data rate. According to the invention, data frames are generated and decomposed at lower data rates than the rate for which the framing circuitry was originally designed, i.e., the first data rate. The framing circuitry is programmed to organize a data stream into a sequence of data frames of the first duration or to decompose such data frames into a data stream. According to the invention, such a sequence of data frames corresponds to a selected one of a plurality of equivalent data rates. Each of the equivalent data rates are lower than the first data rate.

Abstract: An apparatus and method are provided for generating a plurality of data frames in a DSL modem configured as an HTU-C device using a single clock source. The technique of the present invention generates a data clock signal by combining a first clock signal provided by a clock source and a receiver overhead signal provided by framing circuitry for indicating the insertion of frame overhead bits into a data frame. The generated data clock signal has the characteristics such that, while the receiver overhead signal is inactive, the data clock signal is active at a frequency substantially equal to frequency of the first clock signal, and while the receiver overhead signal is active, the data clock signal is inactive. The result of this technique is that incoming data is clocked into the data frame at a data rate substantially equal to the frequency of the first clock signal only during time intervals when frame overhead bits are not being inserted into the one data frame.

Abstract: An apparatus and method are provided for generating a plurality of data frames in a DSL modem configured as an HTU-C device using a single clock source. The technique of the present invention generates a data clock signal by combining a first clock signal provided by a clock source and a receiver overhead signal provided by framing circuitry for indicating the insertion of frame overhead bits into a data frame. The generated data clock signal has the characteristics such that, while said receiver overhead signal is inactive, said data clock signal is active at a frequency substantially equal to frequency of the first clock signal, and while the receiver overhead signal is active, the data clock signal is inactive. The result of this technique is that incoming data is clocked into the data frame at a data rate substantially equal to the frequency of the first clock signal only during time intervals when frame overhead bits are not being inserted into the one data frame.