Abstract: A method for receiving packet data at a communication channel and transmitting the packet data over serial links of the communication channel. The packet data is sliced into n-bit data portions which are concatenated with a header prior to transmitting an n-bit portion across one of the serial links of the communication channel. The header may include an invert bit to alter the majority sign of an n-bit portion. Other aspects of the present invention are also described herein.

Abstract: A channel synchronization method in which local serializers serially transmits first n-bit codes, respectively, to remote deserializers, respectively. Also local deserializers serially receive first n-bit codes, respectively, from remote serializers, respectively. One of the first n-bit codes transmitted to one of the remote serializers indicates one of the local deserializers is not link aligned.

Abstract: Network switching and/or routing devices can use multiple priority data streams and queues to support prioritized serial transmission of data from line cards (or the like) through a fabric switch to other line cards (or the like). Preemption logic is used to insert within a data stream commands indicating a switch from one priority level data to another. Delimiter commands and combination switch/delimiter commands can also be used. Multiple crossbars are implemented in the fabric switch to support the various data stream priority levels.

Abstract: A channel synchronization method in which local serializers serially transmits first n-bit codes, respectively, to remote deserializers, respectively. Also local deserializers serially receive first n-bit codes, respectively, from remote serializers, respectively. One of the first n-bit codes transmitted to one of the remote serializers indicates one of the local deserializers is not link aligned.

Abstract: A method for receiving packet data at a communication channel and transmitting the packet data over serial links of the communication channel. The packet data is sliced into n-bit data portions which are concatenated with a header prior to transmitting an n-bit portion across one of the serial links of the communication channel. The header may include an invert bit to alter the majority sign of an n-bit portion. Other aspects of the present invention are also described herein.

Abstract: A method for receiving packet data at a communication channel and transmitting the packet data over serial links of the communication channel. The packet data is sliced into n-bit data portions which are concatenated with a header prior to transmitting an n-bit portion across one of the serial links of the communication channel. The header may include an invert bit to alter the majority sign of an n-bit portion. Other aspects of the present invention are also described herein.

Abstract: A channel synchronization method in which local serializers serially transmits first n-bit codes, respectively, to remote deserializers, respectively. Also local deserializers serially receive first n-bit codes, respectively, from remote serializers, respectively. One of the first n-bit codes transmitted to one of the remote serializers indicates one of the local deserializers is not link aligned.

Abstract: Network switching and/or routing devices can use multiple priority data streams and queues to support prioritized serial transmission of data from line cards (or the like) through a fabric switch to other line cards (or the like). Preemption logic is used to insert within a data stream commands indicating a switch from one priority level data to another. Delimiter commands and combination switch/delimiter commands can also be used. Multiple crossbars are implemented in the fabric switch to support the various data stream priority levels.

Abstract: A channel synchronization method in which local serializers serially transmits first n-bit codes, respectively, to remote deserializers, respectively. Also local deserializers serially receive first n-bit codes, respectively, from remote serializers, respectively. One of the first n-bit codes transmitted to one of the remote serializers indicates one of the local deserializers is not link aligned.

Abstract: A method for receiving packet data at a communication channel and transmitting the packet data over serial links of the communication channel. The packet data is sliced into n-bit data portions which are concatenated with a header prior to transmitting an n-bit portion across one of the serial links of the communication channel. The header may include an invert bit to alter the majority sign of an n-bit portion. Other aspects of the present invention are also described herein.

Abstract: An apparatus including a first buffer, a second buffer and a priority switch circuit. The first buffer is configured to store data of a first data stream having a first priority. The second buffer is configured to store data of a second data stream having a second priority. The priority switch circuit is coupled to the first buffer and the second buffer and is configured to interrupt a transmission of the first data stream from the first buffer upon detection of data of the second data stream and transmit data of the second data stream.

Abstract: A method for receiving packet data at a communication channel and transmitting the packet data over serial links of the communication channel. The packet data is sliced into n-bit data portions which are concatenated with a header prior to transmitting an n-bit portion across one of the serial links of the communication channel. The header may include an invert bit to alter the majority sign of an n-bit portion. Other aspects of the present invention are also described herein.

Abstract: Network switching and/or routing devices can use multiple priority data streams and queues to support prioritized serial transmission of data from line cards (or the like) through a fabric switch to other line cards (or the like). Preemption logic is used to insert within a data stream commands indicating a switch from one priority level data to another. Delimiter commands and combination switch/delimiter commands can also be used. Multiple crossbars are implemented in the fabric switch to support the various data stream priority levels.

Abstract: A channel synchronization method in which local serializers serially transmits first n-bit codes, respectively, to remote deserializers, respectively. Also local deserializers serially receive first n-bit codes, respectively, from remote serializers, respectively. One of the first n-bit codes transmitted to one of the remote serializers indicates one of the local deserializers is not link aligned.

Abstract: Network switching and/or routing devices can use switching fabrics that gather information about output port buffer status and distribute that information to various line cards for use in data frame congestion avoidance. The switching fabric can gather output buffer status information for all output ports and distribute that information to each line card in an efficient, in-band manner. Individual line cards can use the information to determine from which line card virtual output queue to dequeue data frames destined for the switching fabric. Line cards can also gather output buffer status information associated with line card queues used for receiving data from the switching fabric. Such data is used in a manner similar to the output buffer data from the switching fabric.

Abstract: Disclosed is a method and apparatus for synchronizing data in a number of separate integrated circuits. In one embodiment, the apparatus includes a first integrated circuit configured to receive first data, and a second integrated circuit coupled to the first integrated circuit configured to receive second data. The second integrated circuit is separate from the first integrated circuit. The second integrated circuit is further configured to synchronize the second data with the first data. In another embodiment, the apparatus includes a first integrated circuit configured to receive first data, and a second integrated circuit coupled to the first integrated circuit configured to receive second data. The second integrated circuit is separate from the first integrated circuit. The second integrated circuit is further configured to detect when the second data is out of synchronization with the first data.

Abstract: Disclosed is a method and apparatus for synchronizing data. In one embodiment, the apparatus includes a first communication link for transmitting first data and a second communication link for transmitting second data. A circuit coupled to the first and second communication links. The circuit is configured to receive the first and second data. The circuit is configured to synchronously output the first and second data when the first and second data are received by the circuit out of synchronization.

Abstract: Network switching and/or routing devices can use switching fabrics that gather information about output port buffer status and distribute that information to various line cards for use in data frame congestion avoidance. The switching fabric can gather output buffer status information for all output ports and distribute that information to each line card in an efficient, in-band manner. Individual line cards can use the information to determine from which line card virtual output queue to dequeue data frames destined for the switching fabric. Line cards can also gather output buffer status information associated with line card queues used for receiving data from the switching fabric. Such data is used in a manner similar to the output buffer data from the switching fabric.

Abstract: Within a computing system an input/output device connects an input/output bus to an external data port. Data is transferred between the input/output bus and the external data port. A controller within the input/output device transfers data between the external data port and an internal memory. Direct memory access circuitry within the input/output device transfers data between the internal memory and the input/output bus in synchronization with data transfer across the input/output bus. Data transfers to and from the internal memory are arbitrated so that the controller does not transfer data between the external data port and the internal memory simultaneous to the direct memory access circuitry transferring data between the internal memory and the input/output bus.