Abstract: A protection circuit (100, 700) is disclosed for protecting an integrated circuit having a first supply rail (Vcc) and a second supply rail (Vss) from exposure to an excessive voltage. The protection circuit (100, 700) comprises a sensor (120) for sensing a voltage increase on the first supply rail (Vcc). Such a sensor may be implemented as an RC element. The sensor (120) has an output coupled to a signal path for providing a detection signal on said path. The sensor (120) triggers a clamping circuit (180) to clamp the first supply rail (Vcc) to the second supply rail (Vss) in response to the detection signal, which typically signals an ESD event on the supply rails. A pre-amplifying stage (160) is coupled between the sensor (120) and the clamping circuit (180) to amplify the detection signal for the clamping circuit (180). The protection circuit further comprises a hold circuit (140) for holding the control input of the pre-amplifying stage (160) in an enabled state upon termination of the detection signal.

Abstract: A signal processing module with a timing comparator such as a time to digital converter is provided. The timing comparator comprises an error cancellation stage to remove a predicted effect of the imparted jitter from the timing comparator output signal. A jitter detector is used to detect the jitter from the comparator output signal, preferably residual jitter after the predicted effect of the jitter has been removed. Synchronous detection, such as correlation with the predicted jitter may be used to detect the jitter. The jitter detector adjusts a calibration factor of the timing comparator dependent on the detected jitter.

Abstract: A signal processing module with a timing comparator such as a time to digital converter is provided. The module may be part of a phase locked loop with a fractional frequency divider that acts to produce a divided down signal modulated with jitter in its timing. The timing comparator comprises an error cancellation stage (30, 24.1, 2060) to remove a predicted effect of the imparted jitter from the timing comparator output signal. A jitter detector (80, 1046, 2064) is used to detect the jitter from the comparator output signal, preferably residual jitter after the predicted effect of the jitter has been removed. Synchronous detection, such as correlation with the predicted jitter may be used to detect the jitter. The jitter detector (80, 1046, 2064) adjusts a calibration factor of the timing comparator dependent on the detected jitter.

Abstract: A protection circuit (100, 700) is disclosed for protecting an integrated circuit having a first supply rail (Vcc) and a second supply rail (Vss) from exposure to an excessive voltage. The protection circuit (100, 700) comprises a sensor (120) for sensing a voltage increase on the first supply rail (Vcc). Such a sensor may be implemented as an RC element. The sensor (120) has an output coupled to a signal path for providing a detection signal on said path. The sensor (120) triggers a clamping circuit (180) to clamp the first supply rail (Vcc) to the second supply rail (Vss) in response to the detection signal, which typically signals an ESD event on the supply rails. A pre-amplifying stage (160) is coupled between the sensor (120) and the clamping circuit (180) to amplify the detection signal for the clamping circuit (180). The protection circuit further comprises a hold circuit (140) for holding the control input of the pre-amplifying stage (160) in an enabled state upon termination of the detection signal.