Patents by Inventor Mickael MALABRY
Mickael MALABRY has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11508725Abstract: A CMOS device with a plurality of PMOS transistors each having a PMOS drain and a plurality of NMOS transistors each having an NMOS drain includes a first interconnect and a second interconnect. The first interconnect is on an interconnect level extending in a length direction to connect the PMOS drains together, and the second interconnect is on the interconnect level extending in the length direction to connect the NMOS drains together. A set of interconnects on at least one additional interconnect level physically couple the first interconnect and the second interconnect to an output of the CMOS device. A third interconnect on the interconnect level extends perpendicular to the length direction and offset from the set of interconnects. The third interconnect is capable of flowing current from the PMOS drains or from the NMOS drains to the output of the CMOS device.Type: GrantFiled: January 30, 2020Date of Patent: November 22, 2022Assignee: QUALCOMM INCORPORATEDInventors: Seid Hadi Rasouli, Michael Joseph Brunolli, Christine Sung-An Hau-Riege, Mickael Malabry, Sucheta Kumar Harish, Prathiba Balasubramanian, Kamesh Medisetti, Nikolay Bomshtein, Animesh Datta, Ohsang Kwon
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Patent number: 11133803Abstract: A MOS device of an IC includes pMOS and nMOS transistors. The MOS device further includes a first Mx layer interconnect extending in a first direction and coupling the pMOS and nMOS transistor drains together, and a second Mx layer interconnect extending in the first direction and coupling the pMOS and nMOS transistor drains together. The first and second Mx layer interconnects are parallel. The MOS device further includes a first Mx+1 layer interconnect extending in a second direction orthogonal to the first direction. The first Mx+1 layer interconnect is coupled to the first Mx layer interconnect and the second Mx layer interconnect. The MOS device further includes a second Mx+1 layer interconnect extending in the second direction. The second Mx+1 layer interconnect is coupled to the first Mx layer interconnect and the second Mx layer interconnect. The second Mx+1 layer interconnect is parallel to the first Mx+1 layer interconnect.Type: GrantFiled: May 7, 2020Date of Patent: September 28, 2021Assignee: QUALCOMM IncorporatedInventors: Satyanarayana Sahu, Xiangdong Chen, Venugopal Boynapalli, Hyeokjin Lim, Mickael Malabry, Mukul Gupta
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Patent number: 10965289Abstract: A MOS device of an IC includes pMOS and nMOS transistors. The MOS device further includes a first Mx layer interconnect extending in a first direction and coupling the pMOS and nMOS transistor drains together, and a second Mx layer interconnect extending in the first direction and coupling the pMOS and nMOS transistor drains together. The first and second Mx layer interconnects are parallel. The MOS device further includes a first Mx+1 layer interconnect extending in a second direction orthogonal to the first direction. The first Mx+1 layer interconnect is coupled to the first Mx layer interconnect and the second Mx layer interconnect. The MOS device further includes a second Mx+1 layer interconnect extending in the second direction. The second Mx+1 layer interconnect is coupled to the first Mx layer interconnect and the second Mx layer interconnect. The second Mx+1 layer interconnect is parallel to the first Mx+1 layer interconnect.Type: GrantFiled: February 4, 2019Date of Patent: March 30, 2021Assignee: QUALCOMM IncorporatedInventors: Satyanarayana Sahu, Xiangdong Chen, Venugopal Boynapalli, Hyeokjin Lim, Mickael Malabry, Mukul Gupta
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Publication number: 20200266821Abstract: A MOS device of an IC includes pMOS and nMOS transistors. The MOS device further includes a first Mx layer interconnect extending in a first direction and coupling the pMOS and nMOS transistor drains together, and a second Mx layer interconnect extending in the first direction and coupling the pMOS and nMOS transistor drains together. The first and second Mx layer interconnects are parallel. The MOS device further includes a first Mx+1 layer interconnect extending in a second direction orthogonal to the first direction. The first Mx+1 layer interconnect is coupled to the first Mx layer interconnect and the second Mx layer interconnect. The MOS device further includes a second Mx+1 layer interconnect extending in the second direction. The second Mx+1 layer interconnect is coupled to the first Mx layer interconnect and the second Mx layer interconnect. The second Mx+1 layer interconnect is parallel to the first Mx+1 layer interconnect.Type: ApplicationFiled: May 7, 2020Publication date: August 20, 2020Inventors: Satyanarayana SAHU, Xiangdong CHEN, Venugopal BOYNAPALLI, Hyeokjin LIM, Mickael MALABRY, Mukul GUPTA
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Publication number: 20200168604Abstract: A CMOS device with a plurality of PMOS transistors each having a PMOS drain and a plurality of NMOS transistors each having an NMOS drain includes a first interconnect and a second interconnect. The first interconnect is on an interconnect level extending in a length direction to connect the PMOS drains together, and the second interconnect is on the interconnect level extending in the length direction to connect the NMOS drains together. A set of interconnects on at least one additional interconnect level physically couple the first interconnect and the second interconnect to an output of the CMOS device. A third interconnect on the interconnect level extends perpendicular to the length direction and offset from the set of interconnects. The third interconnect is capable of flowing current from the PMOS drains or from the NMOS drains to the output of the CMOS device.Type: ApplicationFiled: January 30, 2020Publication date: May 28, 2020Inventors: Seid Hadi RASOULI, Michael Joseph BRUNOLLI, Christine Sung-An HAU-RIEGE, Mickael MALABRY, Sucheta Kumar HARISH, Prathiba BALASUBRAMANIAN, Kamesh MEDISETTI, Nikolay BOMSHTEIN, Animesh DATTA, Ohsang KWON
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Patent number: 10605859Abstract: A MOS IC includes a first standard cell including first and second power rails, first and second active regions, and a plurality of metal interconnects. The first power rail extends in a first direction and provides a first voltage to the first standard cell. The second power rail extends in the first direction and provides a second voltage to the first standard cell. The first active region is between the first and second power rails on a first side of the first standard cell. The second active region is between the first and second power rails on a second side of the first standard cell. The second active region is separated from the first active region. The plurality of metal interconnects extend in a second direction between the first and second active regions and between the first and second power rails. The second direction is orthogonal to the first direction.Type: GrantFiled: September 14, 2016Date of Patent: March 31, 2020Assignee: QUALCOMM IncorporatedInventors: Rami Salem, Lesly Zaren V. Endrinal, Hyeokjin Lim, Hadi Bunnalim, Robert Kim, Lavakumar Ranganathan, Mickael Malabry
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Patent number: 10600785Abstract: A CMOS device with a plurality of PMOS transistors and a plurality of NMOS transistors includes a first interconnect and a second interconnect on an interconnect level connecting a first subset and a second subset of PMOS drains together, respectively. The first and second subsets are different and the first and second interconnect are disconnected on the interconnect level. A third interconnect and a fourth interconnect on the interconnect level connect a first subset and a second subset of the NMOS drains together, respectively. The third interconnect and the fourth interconnect are disconnected on the interconnect level. The first, second, third, fourth interconnects are coupled together through at least one other interconnect level. Additional interconnects on the interconnect level connect the first and third interconnects together, and the second and fourth interconnects together, to provide parallel current paths with a current path through the at least one other interconnect level.Type: GrantFiled: March 21, 2018Date of Patent: March 24, 2020Assignee: QUALCOMM IncorporatedInventors: Seid Hadi Rasouli, Michael Joseph Brunolli, Christine Sung-An Hau-Riege, Mickael Malabry, Sucheta Kumar Harish, Prathiba Balasubramanian, Kamesh Medisetti, Nikolay Bomshtein, Animesh Datta, Ohsang Kwon
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Publication number: 20190173473Abstract: A MOS device of an IC includes pMOS and nMOS transistors. The MOS device further includes a first Mx layer interconnect extending in a first direction and coupling the pMOS and nMOS transistor drains together, and a second Mx layer interconnect extending in the first direction and coupling the pMOS and nMOS transistor drains together. The first and second Mx layer interconnects are parallel. The MOS device further includes a first Mx+1 layer interconnect extending in a second direction orthogonal to the first direction. The first Mx+1 layer interconnect is coupled to the first Mx layer interconnect and the second Mx layer interconnect. The MOS device further includes a second Mx+1 layer interconnect extending in the second direction. The second Mx+1 layer interconnect is coupled to the first Mx layer interconnect and the second Mx layer interconnect. The second Mx+1 layer interconnect is parallel to the first Mx+1 layer interconnect.Type: ApplicationFiled: February 4, 2019Publication date: June 6, 2019Inventors: Satyanarayana SAHU, Xiangdong CHEN, Venugopal BOYNAPALLI, Hyeokjin LIM, Mickael MALABRY, Mukul GUPTA
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Patent number: 10236886Abstract: A MOS device of an IC includes pMOS and nMOS transistors. The MOS device further includes a first Mx layer interconnect extending in a first direction and coupling the pMOS and nMOS transistor drains together, and a second Mx layer interconnect extending in the first direction and coupling the pMOS and nMOS transistor drains together. The first and second Mx layer interconnects are parallel. The MOS device further includes a first Mx+1 layer interconnect extending in a second direction orthogonal to the first direction. The first Mx+1 layer interconnect is coupled to the first Mx layer interconnect and the second Mx layer interconnect. The MOS device further includes a second Mx+1 layer interconnect extending in the second direction. The second Mx+1 layer interconnect is coupled to the first Mx layer interconnect and the second Mx layer interconnect. The second Mx+1 layer interconnect is parallel to the first Mx+1 layer interconnect.Type: GrantFiled: December 28, 2016Date of Patent: March 19, 2019Assignee: QUALCOMM IncorporatedInventors: Satyanarayana Sahu, Xiangdong Chen, Venugopal Boynapalli, Hyeokjin Lim, Mickael Malabry, Mukul Gupta
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Patent number: 10175571Abstract: In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus for assigning feature colors for a multiple patterning process are provided. The apparatus receives integrated circuit layout information including a set of features and an assigned color of a plurality of colors for each feature of a first subset of features of the set of features. In addition, the apparatus performs color decomposition on a second subset of features to assign colors to features in the second subset of features. The second subset of features includes features in the set of features that are not included in the first subset of features with an assigned color.Type: GrantFiled: June 14, 2016Date of Patent: January 8, 2019Assignee: QUALCOMM IncorporatedInventors: Xiangdong Chen, Hyeokjin Bruce Lim, Ohsang Kwon, Mickael Malabry, Jingwei Zhang, Raymond George Stephany, Haining Yang, Kern Rim, Stanley Seungchul Song, Mukul Gupta, Foua Vang
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Publication number: 20180183439Abstract: A MOS device of an IC includes pMOS and nMOS transistors. The MOS device further includes a first Mx layer interconnect extending in a first direction and coupling the pMOS and nMOS transistor drains together, and a second Mx layer interconnect extending in the first direction and coupling the pMOS and nMOS transistor drains together. The first and second Mx layer interconnects are parallel. The MOS device further includes a first Mx+1 layer interconnect extending in a second direction orthogonal to the first direction. The first Mx+1 layer interconnect is coupled to the first Mx layer interconnect and the second Mx layer interconnect. The MOS device further includes a second Mx+1 layer interconnect extending in the second direction. The second Mx+1 layer interconnect is coupled to the first Mx layer interconnect and the second Mx layer interconnect. The second Mx+1 layer interconnect is parallel to the first Mx+1 layer interconnect.Type: ApplicationFiled: December 28, 2016Publication date: June 28, 2018Inventors: Satyanarayana SAHU, Xiangdong CHEN, Venugopal BOYNAPALLI, Hyeokjin LIM, Mickael MALABRY, Mukul GUPTA
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Patent number: 9972624Abstract: A CMOS device with a plurality of PMOS transistors each having a PMOS drain and a plurality of NMOS transistors each having an NMOS drain includes a first interconnect on an interconnect level extending in a length direction to connect the PMOS drains together. A second interconnect on the interconnect level extends in the length direction to connect the NMOS drains together. A set of interconnects on at least one additional interconnect level couple the first interconnect and the second interconnect together. A third interconnect on the interconnect level extends perpendicular to the length direction and is offset from the set of interconnects to connect the first interconnect and the second interconnect together.Type: GrantFiled: August 23, 2013Date of Patent: May 15, 2018Assignee: QUALCOMM IncorporatedInventors: Seid Hadi Rasouli, Michael Joseph Brunolli, Christine Sung-An Hau-Riege, Mickael Malabry, Sucheta Kumar Harish, Prathiba Balasubramanian, Kamesh Medisetti, Nikolay Bomshtein, Animesh Datta, Ohsang Kwon
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Patent number: 9935100Abstract: In certain aspects, a semiconductor die includes a power rail, a first gate, and a second gate. The semiconductor die also includes a first gate contact electrically coupled to the first gate, wherein the first gate contact is formed from a first middle of line (MOL) metal layer, and a second gate contact electrically coupled to the second gate, wherein the second gate contact is formed from the first MOL metal layer. The semiconductor die further includes an interconnect formed from a second MOL metal layer, wherein the interconnect is electrically coupled to the first and second gate contacts, and at least a portion of the interconnect is underneath the power rail.Type: GrantFiled: November 9, 2015Date of Patent: April 3, 2018Assignee: QUALCOMM IncorporatedInventors: Hyeokjin Bruce Lim, Zhengyu Duan, Qi Ye, Mickael Malabry
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Publication number: 20180074117Abstract: A MOS IC includes a first standard cell including first and second power rails, first and second active regions, and a plurality of metal interconnects. The first power rail extends in a first direction and provides a first voltage to the first standard cell. The second power rail extends in the first direction and provides a second voltage to the first standard cell. The first active region is between the first and second power rails on a first side of the first standard cell. The second active region is between the first and second power rails on a second side of the first standard cell. The second active region is separated from the first active region. The plurality of metal interconnects extend in a second direction between the first and second active regions and between the first and second power rails. The second direction is orthogonal to the first direction.Type: ApplicationFiled: September 14, 2016Publication date: March 15, 2018Inventors: Rami SALEM, Lesly Zaren V. ENDRINAL, Hyeokjin LIM, Hadi BUNNALIM, Robert KIM, Lavakumar RANGANATHAN, Mickael MALABRY
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Publication number: 20170133365Abstract: In certain aspects, a semiconductor die includes a power rail, a first gate, and a second gate. The semiconductor die also includes a first gate contact electrically coupled to the first gate, wherein the first gate contact is formed from a first middle of line (MOL) metal layer, and a second gate contact electrically coupled to the second gate, wherein the second gate contact is formed from the first MOL metal layer. The semiconductor die further includes an interconnect formed from a second MOL metal layer, wherein the interconnect is electrically coupled to the first and second gate contacts, and at least a portion of the interconnect is underneath the power rail.Type: ApplicationFiled: November 9, 2015Publication date: May 11, 2017Inventors: Hyeokjin Bruce Lim, Zhengyu Duan, Qi Ye, Mickael Malabry
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Publication number: 20160370699Abstract: In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus for assigning feature colors for a multiple patterning process are provided. The apparatus receives integrated circuit layout information including a set of features and an assigned color of a plurality of colors for each feature of a first subset of features of the set of features. In addition, the apparatus performs color decomposition on a second subset of features to assign colors to features in the second subset of features. The second subset of features includes features in the set of features that are not included in the first subset of features with an assigned color.Type: ApplicationFiled: June 14, 2016Publication date: December 22, 2016Inventors: Xiangdong CHEN, Hyeokjin Bruce LIM, Ohsang KWON, Mickael MALABRY, Jingwei ZHANG, Raymond George STEPHANY, Haining YANG, Kern RIM, Stanley Seungchul SONG, Mukul GUPTA, Foua VANG
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Publication number: 20150054568Abstract: A CMOS device with a plurality of PMOS transistors each having a PMOS drain and a plurality of NMOS transistors each having an NMOS drain includes a first interconnect on an interconnect level extending in a length direction to connect the PMOS drains together. A second interconnect on the interconnect level extends in the length direction to connect the NMOS drains together. A set of interconnects on at least one additional interconnect level couple the first interconnect and the second interconnect together. A third interconnect on the interconnect level extends perpendicular to the length direction and is offset from the set of interconnects to connect the first interconnect and the second interconnect together.Type: ApplicationFiled: August 23, 2013Publication date: February 26, 2015Applicant: QUALCOMM INCORPORATEDInventors: Seid Hadi RASOULI, Michael Joseph BRUNOLLI, Christine Sung-An HAU-RIEGE, Mickael MALABRY, Sucheta Kumar HARISH, Prathiba BALASUBRAMANIAN, Kamesh MEDISETTI, Nikolay BOMSHTEIN, Animesh DATTA, Ohsang KWON