Patents by Inventor Mickey Ken

Mickey Ken has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Strain silicon wafer with a crystal orientation (100) in flip chip BGA package
    Patent number: 7851916
    Abstract: A method and system is disclosed for better packaging semiconductor devices. In one example, a semiconductor device package comprises a package substrate, at least one die with an orientation of <100> placed on the substrate with electrical connections made between the package substrate and the die, and an underfill fillet attaching the die to the substrate with the underfill fillet reaching less than 60% of a thickness of the die on at least one side thereof.
    Type: Grant
    Filed: March 17, 2005
    Date of Patent: December 14, 2010
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsin-Hui Lee, Mickey Ken, Chien-Hsiun Lee, Szu Wei Lu
  • Strain silicon wafer with a crystal orientation (100) in flip chip BGA package
    Publication number: 20060208352
    Abstract: A method and system is disclosed for better packaging semiconductor devices. In one example, a semiconductor device package comprises a package substrate, at least one die with an orientation of <100> placed on the substrate with electrical connections made between the package substrate and the die, and an underfill fillet attaching the die to the substrate with the underfill fillet reaching less than 60% of a thickness of the die on at least one side thereof.
    Type: Application
    Filed: March 17, 2005
    Publication date: September 21, 2006
    Inventors: Hsin-Hui Lee, Mickey Ken, Chien-Hsiun Lee, Szu Lu
  • Complementary field-effect transistors and methods of manufacture
    Publication number: 20050116360
    Abstract: A complementary FET and a method of manufacture is provided. The complementary FET utilizes a substrate having a surface layer with a <100> crystal orientation. Tensile stress, which increases performance of the NMOS FETs, is added by silicided source/drain regions, tensile-stress film, shallow trench isolations, inter-layer dielectric, or the like.
    Type: Application
    Filed: July 21, 2004
    Publication date: June 2, 2005
    Inventors: Chien-Chao Huang, Fu-Liang Yang, Mickey Ken, Chenming Hu, Chung-Hu Ge, Wen-Chin Lee, Chih-Hsin Ko