Abstract: A computer system and method for sequencing deoxyribonucleic acid (DNA), to determine the order of the different nucleotides in a genomic sequence or sequence fragment. An alignment system employs a direct “brute force” Hamming distance calculation between a read sequence and a reference genome. The alignment system is configured to compare directly a set of DNA fragments to a reference genome in a short period, and with the higher probability of accuracy than similar comparison systems given the same number of clock cycles. Each DNA fragment is compared with a reference genome for the entire length of the latter using arrangements of memory cells for storing read sequences and inverse complements of the read sequences, shift registers for streaming the reference genome, and circuitry for calculating and summing the distance between the reference, the read sequence, and the inverse complement in parallel. Both digital and analog implementations are described.

Abstract: A computer system and method for sequencing deoxyribonucleic acid (DNA), to determine the order of the different nucleotides in a genomic sequence or sequence fragment. An alignment system employs a direct “brute force” Hamming distance calculation between a read sequence and a reference genome. The alignment system is configured to compare directly a set of DNA fragments to a reference genome in a short period, and with the higher probability of accuracy than similar comparison systems given the same number of clock cycles. Each DNA fragment is compared with a reference genome for the entire length of the latter using arrangements of memory cells for storing read sequences and inverse complements of the read sequences, shift registers for streaming the reference genome, and circuitry for calculating and summing the distance between the reference, the read sequence, and the inverse complement in parallel. Both digital and analog implementations are described.

Abstract: A nonlinear neuron classifier comprising a neuron array including a plurality of neuron chips each including a plurality of neurons of variable length and variable depth, the chips processing input vectors of variable length and variable depth that are input into the classifier for comparison against vectors stored in the classifier, wherein an NSP flag is set for a plurality of the neurons to indicate that only that plurality of neurons is to participate in the vector calculations. A virtual content addressable memory flag is set for certain of the neuron chips to enable functions including fast readout of data from the chips. Results of vector calculations are aggregated for fast readout for a host computer interfacing with the classifier.

Abstract: A nonlinear neuron classifier comprising a neuron array including a plurality of neuron chips each including a plurality of neurons of variable length and variable depth, the chips processing input vectors of variable length and variable depth that are input into the classifier for comparison against vectors stored in the classifier, wherein an NSP flag is set for a plurality of the neurons to indicate that only that plurality of neurons is to participate in the vector calculations. A virtual content addressable memory flag is set for certain of the neuron chips to enable functions including fast readout of data from the chips. Results of vector calculations are aggregated for fast readout for a host computer interfacing with the classifier.

Abstract: A method of queuing erase commands for a nonvolatile memory utilizes placeholder commands to prevent the depth of an operation queue from limiting the number of block erase commands that can be queued at one time. The method includes the step of storing a first erase command in the operation queue. The first erase command is designated as a placeholder erase command if no placeholder command is stored in the operation queue. Each of the first and placeholder erase commands designates at least one block of the nonvolatile memory to be erased. Each block has a corresponding status indicator. If a placeholder erase command is already stored in the operation queue, then 1) the corresponding status indicator for the block designated by the first erase command is set to indicate that the first erase command is an absorbed erase command, and 2) the first erase command is removed from the operation queue.

Abstract: An operation control method and apparatus are described. The apparatus includes a timer circuit, a blocking circuit and a control circuit. The timer circuit provides a done signal upon completion of timing a predetermined elapsed time interval initiated by a start signal. The blocking circuit receives the done signal and provides the done signal as output if the done signal is not blocked when received. The control circuit receives a begin signal indicating that the operation is to be performed and a limit signal to indicate whether or not a condition exists that would prevent the operation from being completed in a single step. If the limit signal indicates the operation can be completed in the single step, the control circuit starts the timing circuit and controls performance of the single step until the done signal is received.

Abstract: An operation control method and apparatus are described. The apparatus includes a timer circuit, a blocking circuit and a control circuit. The timer circuit provides a done signal upon completion of timing a predetermined elapsed time interval initiated by a start signal. The blocking circuit receives the done signal and provides the done signal as output if the done signal is not blocked when received. The control circuit receives a begin signal indicating that the operation is to be performed and a limit signal to indicate whether or not a condition exists that would prevent the operation from being completed in a single step. If the limit signal indicates the operation can be completed in the single step, the control circuit starts the timing circuit and controls performance of the single step until the done signal is received.

Abstract: A method of prioritizing program and erase commands received in an operation queue for a memory includes the step of storing a placeholder erase command in the operation queue. Subsequent erase commands are absorbed by 1) storing the subsequent erase command in the operation queue; 2) setting a corresponding status indicator for the block designated by the subsequent erase command; and 3) removing the subsequent erase command from the operation queue, wherein the subsequent erase command becomes an absorbed erase command. If a program command that designates a same block as any one of the placeholder and absorbed erase commands is stored in the operation queue, then 1) the same block is erased; 2) the status indicator for the same block is cleared, if the same block is associated with the absorbed command; 3) the program command is executed; and 4) the program command is removed from the operation queue.

Abstract: A method of prioritizing program commands relative to erase commands in an operation queue for a memory includes the step of initiating an erase of a first block for a first erase command in the operation queue. The memory has a status indicator for each block. The status indicator indicates whether an erase command for its corresponding block has been received and removed from the operation queue but not yet executed (e.g., an absorbed erase command). An interrupt window is executed during the erasure of the first block to determine if the operation queue has received a second command for a second block. If the second command is a program command, then one of three steps is executed. If the first and second blocks are the same, then execution of the program command is deferred until after the erasure of the first block is complete. If the first and second blocks are not the same then the program command is either executed or deferred in accordance with the status indicator for the second block.

Abstract: A non-volatile memory is described. The memory includes a memory array that includes a main block and a boot block. The memory also includes a control input for receiving a control signal. The control signal can be in a first voltage state, a second voltage state, and a third voltage state. Circuitry means is coupled to receive the control signal at the control input for (1) allowing the boot block to be updated when the control signal is in the first state and for (2) generating a power off signal to switch the memory into a substantially powered off state when the control signal is in the third voltage state. A method of controlling a non-volatile memory is also described.