Abstract: A bit line driver for a static random access memory (SRAM) cell including: a first voltage supply for supplying a first voltage; a second voltage supply for supplying a second voltage that is less than the first voltage; a write circuit to drive a bit line and an inverse bit line when writing to the SRAM cell; and a pre-charge circuit to pre-charge the bit line and the inverse bit line before reading the content of the SRAM cell. The bit line driver supplies a voltage less than the first voltage by a threshold voltage of one transistor to the bit line or the inverse bit line when the bit line driver drives the bit line or the inverse bit line to a high state.

Abstract: A control signal generator to generate control signals for a readout integrated circuit (ROIC) includes a content addressable memory (CAM) and a random access memory (RAM). The CAM may have data stored within it that is indicative of times at which control signal switching events are to occur during generation of the control signals. The RAM may have data stored within it that is indicative of particular control signals that are to be toggled at the times indicated within the CAM.

Abstract: A control signal generator to generate control signals for a readout integrated circuit (ROIC) includes a content addressable memory (CAM) and a random access memory (RAM). The CAM may have data stored within it that is indicative of times at which control signal switching events are to occur during generation of the control signals. The RAM may have data stored within it that is indicative of particular control signals that are to be toggled at the times indicated within the CAM.