Patents by Inventor MIDORI AIZAWA

MIDORI AIZAWA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Logic simulation device
    Patent number: 12197747
    Abstract: A logic simulation device according to an aspect of the present disclosure includes an operation model of a resistance-change memory element. The resistance-change memory element is provided between two terminals. The operation model includes a register section for holding data, a truth table, and a determining section. The truth table defines a relationship between signal values of the two terminals, and data writing to the register section and data reading from the register section. The determining section performs determination about the data writing and the data reading on the basis of signal values inputted to the two terminals and the truth table.
    Type: Grant
    Filed: August 4, 2021
    Date of Patent: January 14, 2025
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Haruko Takahashi, Masami Kuroda, Midori Aizawa
  • Memory system and memory operation
    Patent number: 12148488
    Abstract: A memory system according to an aspect of the present disclosure includes a soft error generator that generates write data or read data considering a probability error by using a specific number as a random number. In the memory system, the write data or the read data considering a probability error is generated by using the random number. Herein, whether or not an error occurs is randomly changed depending on the random number. Accordingly, an error stochastically occurs, which makes it possible to reproduce a soft error.
    Type: Grant
    Filed: May 20, 2021
    Date of Patent: November 19, 2024
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Midori Aizawa, Masami Kuroda, Haruko Takahashi
  • LOGIC SIMULATION DEVICE AND LOGIC SIMULATION PROGRAM
    Publication number: 20230315306
    Abstract: A logic simulation device according to an aspect of the present disclosure includes an operation model of a resistance-change memory element. The resistance-change memory element is provided between two terminals. The operation model includes a register section for holding data, a truth table, and a determining section. The truth table defines a relationship between signal values of the two terminals, and data writing to the register section and data reading from the register section. The determining section performs determination about the data writing and the data reading on the basis of signal values inputted to the two terminals and the truth table.
    Type: Application
    Filed: August 4, 2021
    Publication date: October 5, 2023
    Inventors: HARUKO TAKAHASHI, MASAMI KURODA, MIDORI AIZAWA
  • MEMORY SYSTEM AND MEMORY OPERATION PROGRAM
    Publication number: 20230260587
    Abstract: A memory system according to an aspect of the present disclosure includes a soft error generator that generates write data or read data considering a probability error by using a random number.
    Type: Application
    Filed: May 20, 2021
    Publication date: August 17, 2023
    Inventors: MIDORI AIZAWA, MASAMI KURODA, HARUKO TAKAHASHI