Patents by Inventor Midori Morooka
Midori Morooka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11380397Abstract: Apparatuses are described that include stacked arrays of memory cell strings and their methods of operation. Apparatuses include architectures that reduce the use of several common components, allowing greater device density and smaller device size for a given semiconductor area.Type: GrantFiled: October 9, 2020Date of Patent: July 5, 2022Assignee: Micron Technology, Inc.Inventors: Midori Morooka, Tomoharu Tanaka
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Publication number: 20210098065Abstract: Apparatuses are described that include stacked arrays of memory cell strings and their methods of operation. Apparatuses include architectures that reduce the use of several common components, allowing greater device density and smaller device size for a given semiconductor area.Type: ApplicationFiled: October 9, 2020Publication date: April 1, 2021Inventors: Midori Morooka, Tomoharu Tanaka
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Patent number: 10803944Abstract: Apparatuses are described that include stacked arrays of memory cell strings and their methods of operation. Apparatuses include architectures that reduce the use of several common components, allowing greater device density and smaller device size for a given semiconductor area.Type: GrantFiled: April 8, 2019Date of Patent: October 13, 2020Assignee: Micron Technology, Inc.Inventors: Midori Morooka, Tomoharu Tanaka
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Publication number: 20200005869Abstract: Apparatuses are described that include stacked arrays of memory cell strings and their methods of operation. Apparatuses include architectures that reduce the use of several common components, allowing greater device density and smaller device size for a given semiconductor area.Type: ApplicationFiled: April 8, 2019Publication date: January 2, 2020Inventors: Midori Morooka, Tomoharu Tanaka
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Patent number: 10269429Abstract: Apparatuses are described that include stacked arrays of memory cell strings and their methods of operation. Apparatuses include architectures that reduce the use of several common components, allowing greater device density and smaller device size for a given semiconductor area.Type: GrantFiled: February 19, 2015Date of Patent: April 23, 2019Assignee: Micron Technology, Inc.Inventors: Midori Morooka, Tomoharu Tanaka
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Publication number: 20150162084Abstract: Apparatuses are described that include stacked arrays of memory cell strings and their methods of operation. Apparatuses include architectures that reduce the use of several common components, allowing greater device density and smaller device size for a given semiconductor area.Type: ApplicationFiled: February 19, 2015Publication date: June 11, 2015Inventors: Midori Morooka, Tomoharu Tanaka
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Patent number: 8964474Abstract: Apparatuses are described that include stacked arrays of memory cell strings and their methods of operation. Apparatuses include architectures that reduce the use of several common components, allowing greater device density and smaller device size for a given semiconductor area.Type: GrantFiled: June 15, 2012Date of Patent: February 24, 2015Assignee: Micron Technology, Inc.Inventors: Midori Morooka, Tomoharu Tanaka
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Publication number: 20130336065Abstract: Apparatuses are described that include stacked arrays of memory cell strings and their methods of operation. Apparatuses include architectures that reduce the use of several common components, allowing greater device density and smaller device size for a given semiconductor area.Type: ApplicationFiled: June 15, 2012Publication date: December 19, 2013Inventors: Midori Morooka, Tomoharu Tanaka
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Patent number: 7675803Abstract: A semiconductor device includes a plurality of semiconductor chips and a memory device. The semiconductor chips are provided in a package. Each of the semiconductor chips includes a memory cell array having memory cells which stores data, an output buffer which outputs data read from the memory cell array to an exterior of the semiconductor chip and a control circuit which controls driving power of the output buffer. The memory device stores the number of semiconductor chips provided in the package. The control circuit controls the driving power according to the number of semiconductor chips stored in the memory device.Type: GrantFiled: April 23, 2007Date of Patent: March 9, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Takahiko Hara, Midori Morooka
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Patent number: 7564713Abstract: The present invention discloses a semiconductor integrated circuit device having nonvolatile semiconductor memory cells, bit lines each connected to one end of the nonvolatile semiconductor memory cells, and a data circuit connected to the bit lines to temporarily store program data for the nonvolatile semiconductor memory cells. During a data write operation, the data circuit changes a potential transferred to each bit line in accordance with a program order of the program data.Type: GrantFiled: April 27, 2006Date of Patent: July 21, 2009Assignee: Kabushiki Kaisha ToshibaInventor: Midori Morooka
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Patent number: 7515473Abstract: A semiconductor memory device includes: a memory cell array; a sense amplifier circuit for reading and writing data of the memory cell array page by page; a verify-judge circuit configured to judge write or erase completion based on the verify-read data held in the sense amplifier circuit; and data latches disposed for the respective columns in the memory cell array to be attached to the verify-judge circuit, into which column separation data are written to serve for excluding the corresponding columns from a verifying object, wherein the column separation data are automatically set in the data latches in an initial set-up mode at a power-on time so that at least a part of inaccessible columns for users are excluded from the verifying object.Type: GrantFiled: September 27, 2007Date of Patent: April 7, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Koichi Fukuda, Midori Morooka, Hiroyuki Dohmae
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Patent number: 7486559Abstract: 2 or more sets of initial setup data specifying different operation conditions are stored in a memory cell array comprising electrically-rewritable non-volatile memory cells arranged therein. A control circuit reads a set of initial setup data out of the 2 or more sets of initial setup data via an sense amplifier circuit based on the area information. The initial setup data is transferred to an initial setup data latch and stored therein.Type: GrantFiled: April 26, 2007Date of Patent: February 3, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Midori Morooka, Koichi Fukuda
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Publication number: 20080025101Abstract: A semiconductor memory device includes: a memory cell array; a sense amplifier circuit for reading and writing data of the memory cell array page by page; a verify-judge circuit configured to judge write or erase completion based on the verify-read data held in the sense amplifier circuit; and data latches disposed for the respective columns in the memory cell array to be attached to the verify-judge circuit, into which column separation data are written to serve for excluding the corresponding columns from a verifying object, wherein the column separation data are automatically set in the data latches in an initial set-up mode at a power-on time so that at least a part of inaccessible columns for users are excluded from the verifying object.Type: ApplicationFiled: September 27, 2007Publication date: January 31, 2008Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Koichi Fukuda, Midori Morooka, Hiroyuki Dohmae
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Publication number: 20070253254Abstract: 2 or more sets of initial setup data specifying different operation conditions are stored in a memory cell array comprising electrically-rewritable non-volatile memory cells arranged therein. A control circuit reads a set of initial setup data out of the 2 or more sets of initial setup data via an sense amplifier circuit based on the area information. The initial setup data is transferred to an initial setup data latch and stored therein.Type: ApplicationFiled: April 26, 2007Publication date: November 1, 2007Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Midori MOROOKA, Koichi FUKUDA
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Publication number: 20070246807Abstract: A semiconductor device includes a plurality of semiconductor chips and a memory device. The semiconductor chips are provided in a package. Each of the semiconductor chips includes a memory cell array having memory cells which stores data, an output buffer which outputs data read from the memory cell array to an exterior of the semiconductor chip and a control circuit which controls driving power of the output buffer. The memory device stores the number of semiconductor chips provided in the package. The control circuit controls the driving power according to the number of semiconductor chips stored in the memory device.Type: ApplicationFiled: April 23, 2007Publication date: October 25, 2007Inventors: Takahiko Hara, Midori Morooka
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Patent number: 7277325Abstract: A semiconductor memory device includes: a memory cell array; a sense amplifier circuit for reading and writing data of the memory cell array page by page; a verify-judge circuit configured to judge write or erase completion based on the verify-read data held in the sense amplifier circuit; and data latches disposed for the respective columns in the memory cell array to be attached to the verify-judge circuit, into which column separation data are written to serve for excluding the corresponding columns from a verifying object, wherein the column separation data are automatically set in the data latches in an initial set-up mode at a power-on time so that at least a part of inaccessible columns for users are excluded from the verifying object.Type: GrantFiled: April 28, 2006Date of Patent: October 2, 2007Assignee: Kabushiki Kaisha ToshibaInventors: Koichi Fukuda, Midori Morooka, Hiroyuki Dohmae
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Publication number: 20060245261Abstract: The present invention discloses a semiconductor integrated circuit device having nonvolatile semiconductor memory cells, bit lines each connected to one end of the nonvolatile semiconductor memory cells, and a data circuit connected to the bit lines to temporarily store program data for the nonvolatile semiconductor memory cells. During a data write operation, the data circuit changes a potential transferred to each bit line in accordance with a program order of the program data.Type: ApplicationFiled: April 27, 2006Publication date: November 2, 2006Inventor: Midori Morooka
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Publication number: 20060245259Abstract: A semiconductor memory device includes: a memory cell array; a sense amplifier circuit for reading and writing data of the memory cell array page by page; a verify-judge circuit configured to judge write or erase completion based on the verify-read data held in the sense amplifier circuit; and data latches disposed for the respective columns in the memory cell array to be attached to the verify-judge circuit, into which column separation data are written to serve for excluding the corresponding columns from a verifying object, wherein the column separation data are automatically set in the data latches in an initial set-up mode at a power-on time so that at least a part of inaccessible columns for users are excluded from the verifying object.Type: ApplicationFiled: April 28, 2006Publication date: November 2, 2006Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Koichi Fukuda, Midori Morooka, Hiroyuki Dohmae