Abstract: According to one embodiment, a device includes a first substrate including first and second gate lines which extend in a first direction, a source line which extends in a second direction, and a pixel electrode including a primary pixel electrode which is located between the first and second gate lines and which extends in the second direction, a second substrate including a common electrode which extends parallel to the primary pixel electrode on both sides across the primary pixel electrode, and a liquid crystal layer held between the first and second substrates. At a position that intersects with the source line, at least one of the first gate line and the second gate line includes a depression provided in an end located on the side of the pixel electrode.

Abstract: According to one embodiment, a device includes a first substrate including first and second gate lines which extend in a first direction, a source line which extends in a second direction, and a pixel electrode including a primary pixel electrode which is located between the first and second gate lines and which extends in the second direction, a second substrate including a common electrode which extends parallel to the primary pixel electrode on both sides across the primary pixel electrode, and a liquid crystal layer held between the first and second substrates. At a position that intersects with the source line, at least one of the first gate line and the second gate line includes a depression provided in an end located on the side of the pixel electrode.

Abstract: An aspect of the present invention provides a phase interpolator for adjusting a phase of differential clock signals of a receiver to a phase of a data from a transmitter that includes, an integrator configured to slew edges of differential clock signals adjusted to the phase of the data from the transmitter, a output buffer configured to amplify an output of the integrator, a duty cycle correction circuit configured to feed duty correction signals back to the adjusted differential clock signals, and a controller configured to ensure operations of an amplitude of the output buffer and a data read circuit to adjust the swings and duties of the adjusted differential clock signals.

Abstract: An aspect of the present invention provides a phase interpolator for adjusting a phase of differential clock signals of a receiver to a phase of a data from a transmitter that includes, an integrator configured to slew edges of differential clock signals adjusted to the phase of the data from the transmitter, a output buffer configured to amplify an output of the integrator, a duty cycle correction circuit configured to feed duty correction signals back to the adjusted differential clock signals, and a controller configured to ensure operations of an amplitude of the output buffer and a data read circuit to adjust the swings and duties of the adjusted differential clock signals.

Abstract: A method optimizes a tree depth of an H-tree network for distributing a clock signal to elements of a semiconductor integrated circuit, in a way as to minimize power consumption of the H-tree network. The method has the steps of entering parameters, defining a short circuit current component PS, cell internal switching current component PI, and switching current of interconnect capacitance component PW of the power consumption of the H-tree network with equations employing a tree depth m as a variable, defining the power consumption F of the H-tree network as the sum of the components PS, PI, and PW, and finding a tree depth that minimizes the power consumption F. The method differentiates the power consumption F, i.e., the sum of the components PS, PI, and PW with respect to the tree depth m as ∂F/∂m and solves “∂F/∂m=0” to find the optimum tree depth of the H-tree network.

Abstract: A method wires devices formed on a semiconductor integrated circuit. The method includes the steps of finding a wiring path between the devices, determining whether or not a delay in transmitting signals through the wiring path is within a predetermined range, and if the delay is out of the constraint, changing the number, or area, or both of them of through-holes of a given via in the wiring path so that the delay meets in the timing constraints. The integrated circuit thus wired is capable of handling signals that require severe delay specifications.

Abstract: A layout method of designing a wiring pattern on a semiconductor integrated circuit chip according to the present invention comprises three steps of omitting a part of or all of a wiring pattern within cells for a plurality of circuit elements for layout results of these predetermined circuit elements to prepare wiring obstruction data (step 1); deciding a specific wiring path connecting between the cells with reference to the prepared wiring obstruction data (step 2); and repositioning of the cell to correct the layout with no design rule violation and no short between this specific wiring path and the wiring pattern within cells (step 3). The pattern layout is performed so that the specific wiring path is wired in the shortest length of wiring path without making a snaking wire path and also uncomplete wiring does not happen to occur.