Patents by Inventor Mieko Hasegawa
Mieko Hasegawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210342876Abstract: The present invention provides a registration system (100) including an acquisition unit (10) that acquires an image including a product from a imaging unit, and an output unit (30) that outputs, when at least a part of a mark including discount information related to the product is included in the image, but the discount information cannot be acquired by an image analysis, guidance information for acquiring the discount information.Type: ApplicationFiled: February 1, 2019Publication date: November 4, 2021Applicant: NEC CORPORATIONInventors: Itsumi HANEDA, Yasuhito OTSUKA, Mieko HASEGAWA
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Patent number: 8329584Abstract: A post-CMP cleaning process of a copper layer is to be performed as follows. An alkaline aqueous solution, a polycarboxylic acid, BTA, and an alkaline aqueous solution are sequentially brought into contact with a primary surface of a silicon substrate over which the copper layer is provided.Type: GrantFiled: June 2, 2011Date of Patent: December 11, 2012Assignee: Renesas Electronics CorporationInventors: Toshiyuki Takewaki, Manabu Iguchi, Daisuke Oshida, Hironori Toyoshima, Masayuki Hiroi, Takuji Onuma, Hiroaki Nanba, Ichiro Honma, Mieko Hasegawa, Yasuaki Tsuchiya, Toshiji Taiji, Takaharu Kunugi
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Publication number: 20110230051Abstract: A post-CMP cleaning process of a copper layer is to be performed as follows. An alkaline aqueous solution, a polycarboxylic acid, BTA, and an alkaline aqueous solution are sequentially brought into contact with a primary surface of a silicon substrate over which the copper layer is provided.Type: ApplicationFiled: June 2, 2011Publication date: September 22, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Toshiyuki TAKEWAKI, Manabu IGUCHI, Daisuke OSHIDA, Hironori TOYOSHIMA, Masayuki HIROI, Takuji ONUMA, Hiroaki NANBA, Ichiro HONMA, Mieko HASEGAWA, Yasuaki TSUCHIYA, Toshiji TAIJI, Takaharu KUNUGI
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Patent number: 7955980Abstract: A post-CMP cleaning process of a copper layer is to be performed as follows. An alkaline aqueous solution, a polycarboxylic acid, BTA, and an alkaline aqueous solution are sequentially brought into contact with a primary surface of a silicon substrate over which the copper layer is provided.Type: GrantFiled: August 18, 2009Date of Patent: June 7, 2011Assignee: Renesas Electronics CorporationInventors: Toshiyuki Takewaki, Manabu Iguchi, Daisuke Oshida, Hironori Toyoshima, Masayuki Hiroi, Takuji Onuma, Hiroaki Nanba, Ichiro Honma, Mieko Hasegawa, Yasuaki Tsuchiya, Toshiji Taiji, Takaharu Kunugi
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Patent number: 7687918Abstract: The present invention provides a semiconductor device comprising a metal interconnect having considerably improved electromigration resistance and/or stress migration resistance. The copper interconnect 107 comprises a silicon-lower concentration region 104 and a silicon solid solution layer 106 disposed thereon. The silicon solid solution layer 106 has a structure, in which silicon atoms are introduced within the crystal lattice structure that constitutes the copper interconnect 107 to be disposed within the lattice as inter-lattice point atoms or substituted atoms. The silicon solid solution layer 106 has the structure, in which the crystal lattice structure of copper (face centered cubic lattice; lattice constant is 3.6 angstrom) remains, while silicon atoms are introduced as inter-lattice point atoms or substituted atoms.Type: GrantFiled: December 22, 2003Date of Patent: March 30, 2010Assignee: NEC Electronics CorporationInventors: Yorinobu Kunimune, Mieko Hasegawa, Takamasa Itou, Takeshi Takeda, Hidemitsu Aoki
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Publication number: 20090305496Abstract: A post-CMP cleaning process of a copper layer is to be performed as follows. An alkaline aqueous solution, a polycarboxylic acid, BTA, and an alkaline aqueous solution are sequentially brought into contact with a primary surface of a silicon substrate over which the copper layer is provided.Type: ApplicationFiled: August 18, 2009Publication date: December 10, 2009Applicant: NEC ELECTRONICS CORPORATIONInventors: Toshiyuki TAKEWAKI, Manabu IGUCHI, Daisuke OSHIDA, Hironori TOYOSHIMA, Masayuki HIROI, Takuji ONUMA, Hiroaki NANBA, Ichiro HONMA, Mieko HASEGAWA, Yasuaki TSUCHIYA, Toshiji TAIJI, Takaharu KUNUGI
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Patent number: 7629656Abstract: A semiconductor device 1 includes a semiconductor substrate 10, insulating interlayer group 20 (first insulating interlayer group), insulating interlayer group 30 (second insulating interlayer group), and seal ring 40 (guard ring). The insulating interlayer group 20 is formed on the semiconductor substrate 10. The insulating interlayer group 30 is formed on the insulating interlayer group 20. The insulating interlayer group 30 is formed by an insulating material having a lower dielectric constant than that of the insulating interlayer group 20. The seal ring 40 is provided so as to surround the circuit forming regions D11 and D12. The seal ring 40 penetrates through the interface between the insulating interlayer group 20 and the insulating interlayer group 30 and is provided apart from the semiconductor substrate 10.Type: GrantFiled: July 13, 2006Date of Patent: December 8, 2009Assignee: NEC Electronics CorporationInventors: Mieko Hasegawa, Yasutaka Nakashiba
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Patent number: 7601640Abstract: A post-CMP cleaning process of a copper layer is to be performed as follows. An alkaline aqueous solution, a polycarboxylic acid, BTA, and an alkaline aqueous solution are sequentially brought into contact with a primary surface of a silicon substrate over which the copper layer is provided.Type: GrantFiled: December 10, 2007Date of Patent: October 13, 2009Assignee: NEC Electronics CorporationInventors: Toshiyuki Takewaki, Manabu Iguchi, Daisuke Oshida, Hironori Toyoshima, Masayuki Hiroi, Takuji Onuma, Hiroaki Nanba, Ichiro Honma, Mieko Hasegawa, Yasuaki Tsuchiya, Toshiji Taiji, Takaharu Kunugi
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Publication number: 20080160750Abstract: A post-CMP cleaning process of a copper layer is to be performed as follows. An alkaline aqueous solution, a polycarboxylic acid, BTA, and an alkaline aqueous solution are sequentially brought into contact with a primary surface of a silicon substrate over which the copper layer is provided.Type: ApplicationFiled: December 10, 2007Publication date: July 3, 2008Applicant: NEC ELECTRONICS CORPORATIONInventors: Toshiyuki TAKEWAKI, Manabu Iguchi, Daisuke Oshida, Hironori Toyoshima, Masayuki Hiroi, Takuji Onuma, Hiroaki Nanba, Ichiro Honma, Mieko Hasegawa, Yasuaki Tsuchiya, Toshiji Taiji, Takahara Kunugi
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Publication number: 20070018326Abstract: A semiconductor device 1 includes a semiconductor substrate 10, insulating interlayer group 20 (first insulating interlayer group), insulating interlayer group 30 (second insulating interlayer group), and seal ring 40 (guard ring). The insulating interlayer group 20 is formed on the semiconductor substrate 10. The insulating interlayer group 30 is formed on the insulating interlayer group 20. The insulating interlayer group 30 is formed by an insulating material having a lower dielectric constant than that of the insulating interlayer group 20. The seal ring 40 is provided so as to surround the circuit forming regions D11 and D12. The seal ring 40 penetrates through the interface between the insulating interlayer group 20 and the insulating interlayer group 30 and is provided apart from the semiconductor substrate 10.Type: ApplicationFiled: July 13, 2006Publication date: January 25, 2007Applicant: NEC ELECTRONICS CORPORATIONInventors: Mieko Hasegawa, Yasutaka Nakashiba
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Publication number: 20040130030Abstract: The present invention provides a semiconductor device comprising a metal interconnect having considerably improved electromigration resistance and/or stress migration resistance. The copper interconnect 107 comprises a silicon-lower concentration region 104 and a silicon solid solution layer 106 disposed thereon. The silicon solid solution layer 106 has a structure, in which silicon atoms are introduced within the crystal lattice structure that constitutes the copper interconnect 107 to be disposed within the lattice as inter-lattice point atoms or substituted atoms. The silicon solid solution layer 106 has the structure, in which the crystal lattice structure of copper (face centered cubic lattice; lattice constant is 3.6 angstrom) remains, while silicon atoms are introduced as inter-lattice point atoms or substituted atoms.Type: ApplicationFiled: December 22, 2003Publication date: July 8, 2004Applicant: NEC Electronics CorporationInventors: Yorinobu Kunimune, Mieko Hasegawa, Takamasa Itou, Takeshi Takeda, Hidemitsu Aoki
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Patent number: 6350683Abstract: The present invention provides a method of forming a tungsten plug in a hole of an inter-layer insulator. The method comprises the steps of: forming at least a hole in an inter-layer insulator; forming a thin barrier layer on at least an inside face of a hole; carrying out a first chemical vapor deposition process for growing a micro crystal tungsten thin film on the thin barrier layer; carrying out a second chemical vapor deposition process for growing a tungsten layer from the micro crystal tungsten thin film, so that the tungsten layer fills the hole and also extends over a top surface of the inter-layer insulator; and carrying out a chemical mechanical polishing process for selectively removing the tungsten layer over the top surface of the inter-layer insulator and leaving the tungsten layer in the hole, thereby to form a tungsten plug in the hole, wherein the second chemical vapor deposition process is carried out at a substrate temperature of not less than 475° C.Type: GrantFiled: August 23, 2000Date of Patent: February 26, 2002Assignee: NEC CorporationInventor: Mieko Hasegawa
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Patent number: 6100197Abstract: There is provided a method of fabricating a semiconductor device, including the steps of (a) forming recesses at a surface of an underlying insulating film, (b) covering inner surfaces of the recesses and a surface of the underlying insulating film with a barrier film, (c) depositing a copper film over the barrier film to thereby fill the recesses with copper, and (d) applying chemical mechanical polishing (CMP) to the copper film through the use of inorganic slurry on the condition that a polishing load is equal to or smaller than 140 g/cm.sup.2 and a linear velocity at a center of a wafer is equal to or smaller than 0.1 m/s. Though a copper film tends to be peeled off after CMP has been applied thereto in a conventional method, the method ensures that a copper film is no longer peeled off even after CMP has been applied thereto.Type: GrantFiled: October 12, 1999Date of Patent: August 8, 2000Assignee: NEC CorporationInventor: Mieko Hasegawa