Abstract: The present invention provides an artificial blood vessel that can achieve a balance between cell penetration efficiency and crush resistance and can regenerate a blood vessel at very high efficiency. Provided is an artificial blood vessel having a tubular shape, including: a foam containing a bioabsorbable material; a reinforcement A containing a bioabsorbable material; and a reinforcement B including threads containing a bioabsorbable material, the foam being reinforced with the reinforcements A and B, wherein the reinforcement A is a non-woven fabric, a film, or a weft-knitted, warp-knitted, or woven fabric made of knitted or woven fibers, the reinforcement B includes monofilament threads each having a cross-sectional diameter of 0.

Abstract: To solve a problem of realizing a large current and highly reliable power semiconductor device while shrinking a unit cell. A semiconductor device according to the present invention includes a plurality of p-type body regions extending in a first direction. The semiconductor device further includes: a JFET region formed to extend in the first direction between p-type body regions which are adjacent to each other in a second direction orthogonal to the first direction; an n+-type source region formed to extend in the first direction within a p-type body region and separate from an end side surface of the p-type body; and a channel region formed to extend in the first direction and in a top layer portion of a p-type body region between an end side surface of the p-type body region and an end side surface of an n+-type source region.

Abstract: A MOSFET using a SiC substrate has a problem that a carbon-excess layer is formed on a surface by the application of mechanical stress due to thermal oxidation and the carbon-excess layer degrades mobility of channel carriers. In the invention, (1) a layer containing carbon-carbon bonds is removed; (2) a gate insulating film is formed by a deposition method; and (3) an interface between a crystal surface and the insulating film is subjected to an interface treatment at a low temperature for a short time. Due to this, the carbon-excess layer causing characteristic degradation is effectively eliminated, and at the same time, dangling bonds can be effectively eliminated by subjecting an oxide film and an oxynitride film to an interface treatment.

Abstract: A MOSFET using a SiC substrate has a problem that a carbon-excess layer is formed on a surface by the application of mechanical stress due to thermal oxidation and the carbon-excess layer degrades mobility of channel carriers. In the invention, (1) a layer containing carbon-carbon bonds is removed; (2) a gate insulating film is formed by a deposition method; and (3) an interface between a crystal surface and the insulating film is subjected to an interface treatment at a low temperature for a short time. Due to this, the carbon-excess layer causing characteristic degradation is effectively eliminated, and at the same time, dangling bonds can be effectively eliminated by subjecting an oxide film and an oxynitride film to an interface treatment.

Abstract: To solve a problem of realizing a large current and highly reliable power semiconductor device while shrinking a unit cell. A semiconductor device according to the present invention includes a plurality of p-type body regions extending in a first direction. The semiconductor device further includes: a JFET region formed to extend in the first direction between p-type body regions which are adjacent to each other in a second direction orthogonal to the first direction; an n+-type source region formed to extend in the first direction within a p-type body region and separate from an end side surface of the p-type body; and a channel region formed to extend in the first direction and in a top layer portion of a p-type body region between an end side surface of the p-type body region and an end side surface of an n+-type source region.

Abstract: A composition for forming a passivation layer, comprising a compound represented by Formula (I): M(OR1)m. In Formula (I), M comprises at least one metal element selected from the group consisting of Nb, Ta, V, Y and Hf, each R1 independently represents an alkyl group having from 1 to 8 carbon atoms or an aryl group having from 6 to 14 carbon atoms, and m represents an integer from 1 to 5.

Abstract: Provided is a technique of securing reliability of a gate insulating film, as much as in a Si power MOSFET, in a semiconductor device in which a semiconductor material having a larger band gap than silicon is used, and which is typified by, for example, an SiC power MOSFET. In order to achieve this object, in the in the SiC power MOSFET, the gate electrode GE is formed in contact with the gate insulating film GOX, and is formed of the polycrystalline silicon film PF1 having the thickness equal to or smaller than 200 nm, and the polycrystalline silicon film PF2 formed in contact with the polycrystalline silicon film PF1, and having any thickness.

Abstract: A composition for forming a passivation layer, including a resin and a compound represented by Formula (I): M(OR1)m. In Formula (I), M includes at least one metal element selected from the group consisting of Nb, Ta, V, Y and Hf, each R1 independently represents an alkyl group having from 1 to 8 carbon atoms or an aryl group having from 6 to 14 carbon atoms, and m represents an integer from 1 to 5.

Abstract: Provided is a technique of securing reliability of a gate insulating film, as much as in a Si power MOSFET, in a semiconductor device in which a semiconductor material having a larger band gap than silicon is used, and which is typified by, for example, an SiC power MOSFET. In order to achieve this object, in the in the SiC power MOSFET, the gate electrode GE is formed in contact with the gate insulating film GOX, and is formed of the polycrystalline silicon film PF1 having the thickness equal to or smaller than 200 nm, and the polycrystalline silicon film PF2 formed in contact with the polycrystalline silicon film PF1, and having any thickness.

Abstract: A MOSFET using a SiC substrate has a problem that a carbon-excess layer is formed on a surface by the application of mechanical stress due to thermal oxidation and the carbon-excess layer degrades mobility of channel carriers. In the invention, (1) a layer containing carbon-carbon bonds is removed; (2) a gate insulating film is formed by a deposition method; and (3) an interface between a crystal surface and the insulating film is subjected to an interface treatment at a low temperature for a short time. Due to this, the carbon-excess layer causing characteristic degradation is effectively eliminated, and at the same time, dangling bonds can be effectively eliminated by subjecting an oxide film and an oxynitride film to an interface treatment.

Abstract: A solar cell including a substrate 1, a nanopillar 11 having diameter D1 connected to the substrate 1, and a nanopillar 12 having diameter D2 connected to the substrate 1 is characterized in that D2 is greater than D1 in order to realize a solar cell having, as the surface structure, a nanopillar array structure with which it is possible to prevent reflection within the broad wavelength region of solar light. A nanopillar array structure 21 formed from two types of nanopillars having different diameters has a point of minimum reflectivity of a nanopillar array structure formed from the nanopillar 11 having diameter D1 and a point of minimum reflectivity of a nanopillar array structure formed from the nanopillar 12 having diameter D2 and therefore, is capable of preventing reflection within the broad wavelength region of solar light.

Abstract: A composition for forming a passivation layer, including a resin and a compound represented by Formula (I): M(OR1)m. In Formula (I), M includes at least one metal element selected from the group consisting of Nb, Ta, V, Y and Hf, each R1 independently represents an alkyl group having from 1 to 8 carbon atoms or an aryl group having from 6 to 14 carbon atoms, and m represents an integer from 1 to 5.

Abstract: A passivation film includes aluminum oxide and niobium oxide, and the passivation film is used in a photovoltaic cell element having a silicon substrate. A photovoltaic cell element includes: a p-type silicon substrate 1 that comprises monocrystalline silicon or polycrystalline silicon; an n-type impurity diffusion layer 2 that is formed on a light receiving surface of the silicon substrate 1; a first electrode 5 that is formed on the n-type impurity diffusion layer 2; a second electrode 6 that is formed on the back surface of the silicon substrate 1; a passivation film 7 that is formed on the back surface of the silicon substrate 1, the passivation film 7 having plural openings OA and including aluminum oxide and niobium oxide. The second electrode 6 is electrically connected to the back surface of the silicon substrate 1 through the plural openings OA.

Abstract: A composition for forming a passivation layer, comprising a compound represented by Formula (I): M(OR1)m. In Formula (I), M comprises at least one metal element selected from the group consisting of Nb, Ta, V, Y and Hf, each R1 independently represents an alkyl group having from 1 to 8 carbon atoms or an aryl group having from 6 to 14 carbon atoms, and m represents an integer from 1 to 5.

Abstract: A surface reflectivity of a solar cell is reduced by applying a nanopillar array including a plurality of nanopillars to the solar cell. Further, by constituting the nanopillars with a Si/SiGe superlattice and controlling a Ge composition ratio of a SiGe layer (2), excited electron and hole are spatially separated in different layers, thus increasing a carrier lifetime, and at the same time, an optical-electrical conversion efficiency is improved by a multi-exciton phenomenon due to a quantum confinement effect. In addition, by forming an intermediate band by thinning a Si layer (1) and the SiGe layer (2), a carrier extraction efficiency is improved.

Abstract: A solar cell including a substrate 1, a nanopillar 11 having diameter D1 connected to the substrate 1, and a nanopillar 12 having diameter D2 connected to the substrate 1 is characterized in that D2 is greater than D1 in order to realize a solar cell having, as the surface structure, a nanopillar array structure with which it is possible to prevent reflection within the broad wavelength region of solar light. A nanopillar array structure 21 formed from two types of nanopillars having different diameters has a point of minimum reflectivity of a nanopillar array structure formed from the nanopillar 11 having diameter D1 and a point of minimum reflectivity of a nanopillar array structure formed from the nanopillar 12 having diameter D2 and therefore, is capable of preventing reflection within the broad wavelength region of solar light.

Abstract: An image display unit is provided for which it is possible to reduce the number of ion plantation and photolithographic processes required to manufacture the device. A gate electrode GT is a laminated structure of a thin bottom layer metal film GMB and a top layer metal film GMT. A top electrode of a storage capacitor Cst is formed of the bottom layer metal film GMB and ion implantation for the top electrode is performed at the same time as the ion implantation of source-drain electrodes. The gate electrode of a PMOSTFT of the device is also formed with the bottom layer metal GMB, and the ion implantation for threshold adjustment is performed by using the same resist.

Abstract: A display device includes a plurality of thin-film transistors formed on a substrate on which a display area is formed. The display device also includes a gate electrode, a gate insulating film formed so as to cover the gate electrode, an semiconductor layer in an island shape formed on an upper surface of the gate insulating film so as to superimpose the gate electrode without protruding from the gate electrode when viewed planarly, an insulating film formed so as to cover the semiconductor layer, and a pair of electrodes electrically connected to the semiconductor layer respectively through a pair of through holes that are formed at the insulating film. The semiconductor layer is formed by sequentially laminating a crystalline semiconductor layer and an amorphous semiconductor layer. The pair of electrodes is respectively formed by sequentially laminating a semiconductor layer doped with impurities and a metal layer.

Abstract: A bottom gate-type thin film transistor includes a gate insulating film, an interlayer insulating film formed on the gate insulating film, having an opening which is formed in a formation region of a gate electrode, and a semiconductor film formed on the interlayer insulating film so as to cover the opening. The interlayer insulating film contains nitrides in an amount larger than that in the gate insulating film, and the semiconductor film includes a microcrystalline semiconductor film or a polycrystalline semiconductor film formed on semiconductor crystalline nuclei which are formed on the gate insulating film and the interlayer insulating film and contain at least Ge.

Abstract: Provided is a method of promoting a deposition of semiconductor crystal nuclei on an insulating film such as a silicon oxide film even at a low temperature of 450° C. or lower in a reactive thermal CVD method. As one means thereof, a first semiconductor film is formed on an insulating substrate, and then semiconductor crystal nuclei are formed on parts of the first semiconductor film and simultaneously the first semiconductor film other than that in forming regions of the semiconductor crystal nuclei and their peripheries is removed by etching. Thereafter, a second semiconductor film is formed with using the semiconductor crystal nuclei as seeds.