Patents by Inventor Mieu Van Vu

Mieu Van Vu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and system for low power transmission and data alignment
    Patent number: 8964791
    Abstract: A method and apparatus automatically maintains a JESD204 serial data link (252) as active by using an idle signal (254) and multiplexer selection circuit (247) to selectively switch signal data samples (246) and dummy samples (0, . . . 0) onto a serial interface input to a JESD module (248) for serialization into a plurality of symbols for transmission over the JESD204 serial data link (252) in response to a transmit clock signal (253) so that serialized symbols generated from signal data samples are transmitted when there are signal data samples available, and serialized symbols generated from dummy samples are transmitted when there are no signal data samples available.
    Type: Grant
    Filed: October 11, 2012
    Date of Patent: February 24, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Mieu Van Vu, John J. Vaglica
  • Method and System for Low Power Transmission and Data Alignment
    Publication number: 20140105101
    Abstract: A method and apparatus automatically maintains a JESD204 serial data link (252) as active by using an idle signal (254) and multiplexer selection circuit (247) to selectively switch signal data samples (246) and dummy samples (0, . . . 0) onto a serial interface input to a JESD module (248) for serialization into a plurality of symbols for transmission over the JESD204 serial data link (252) in response to a transmit clock signal (253) so that serialized symbols generated from signal data samples are transmitted when there are signal data samples available, and serialized symbols generated from dummy samples are transmitted when there are no signal data samples available.
    Type: Application
    Filed: October 11, 2012
    Publication date: April 17, 2014
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Mieu Van Vu, John J. Vaglica
  • Method and apparatus for entering a low power mode
    Patent number: 7181188
    Abstract: A method and apparatus for entering a low power mode is provided. In one embodiment, data processing system (10) has power control circuitry (52) which may be used to control power usage in data processing system (10). Power mode select circuitry (84) may be used to select a power mode. Depending upon the power mode selected, power control circuitry (52) may use a cascaded approach to selecting which portions of data processing system (10) will be powered down, and thus how deeply data processing system (10) will be powered down.
    Type: Grant
    Filed: March 23, 2004
    Date of Patent: February 20, 2007
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Mieu Van Vu, Christopher K. Chun, Arthur M. Goldberg, David J. Hayes, Charbel Khawand, Jianping Tao, John J. Vaglica