Abstract: A virtual DMA channel technique in which a generally larger number of DMA channels are mapped to a generally smaller number of DMA engines can provide a configuration in which switches amongst DMA engines (and therefore amongst a current working set of DMA channels currently mapped thereto) can be accomplished without context switch latency. Accordingly, as long as contents of the current working set can be appropriately managed, many changes (whether or nor priority based) between a current active DMA channel and a next runnable DMA channel can be accomplished without incurring a context switch latency such as normally associated with loading/restoring and/or saving DMA context information. In some embodiments, a working set or replacement strategy that seeks to cache a most frequently (or most recently) used subset of virtual DMA channels is employed. In some embodiments, a set- or frame-oriented variants of such strategies may be employed.

Abstract: A virtual DMA channel technique in which a generally larger number of DMA channels are mapped to a generally smaller number of DMA engines can provide a configuration in which switches amongst DMA engines (and therefore amongst a current working set of DMA channels currently mapped thereto) can be accomplished without context switch latency. Accordingly, as long as contents of the current working set can be appropriately managed, many changes (whether or nor priority based) between a current active DMA channel and a next runnable DMA channel can be accomplished without incurring a context switch latency such as normally associated with loading/restoring and/or saving DMA context information. In some embodiments, a working set or replacement strategy that seeks to cache a most frequently (or most recently) used subset of virtual DMA channels is employed. In some embodiments, a set- or frame-oriented variants of such strategies may be employed.

Abstract: A method and apparatus for entering a low power mode is provided. In one embodiment, data processing system (10) has power control circuitry (52) which may be used to control power usage in data processing system (10). Power mode select circuitry (84) may be used to select a power mode. Depending upon the power mode selected, power control circuitry (52) may use a cascaded approach to selecting which portions of data processing system (10) will be powered down, and thus how deeply data processing system (10) will be powered down.

Abstract: A processing system that interacts with external devices has a processor, a memory, and a controller. The memory stores templates that provide access protocol information about the external devices. When an external device is to be accessed, the operating system, which is stored in the memory, instructs the processor to perform the access to the external device. The processor puts the information about the external device on the address portion of the system bus where it is received and interpreted by the controller. The controller in turn retrieves the template for the external device as indicated by the information that was received. After retrieving the template, the controller outputs the information, in the manner indicated by the template, on an external interface bus where the external device is also coupled. The external device then responds according to the information that the controller put on the external interface bus.

Abstract: A cellular mobile station including a modem processor and memory. The memory includes instructions for the modem processor to perform layer 1 processor operations, layer 2 processor operations, and layer 3 processor operations. The modem processor executes the instructions to perform processor operations for the cellular mobile station to communication data as per a cellular communications protocol.