Abstract: Semiconductor devices have a substrate including first and second regions of differing conductivity types and a shallow trench isolation isolation region that extends within the first and second regions. First and second active regions are disposed in respective first and second regions, with a gate electrode disposed in a lower portion of a gate groove that extends continuously from the first active region to the second active region, the gate groove being shallower than the shallow trench. A cap insulating film is disposed in an upper portion of the gate groove covering an upper surface of the gate electrode. First and second transistors are within respective first and second active regions and share the gate electrode.

Abstract: A semiconductor device comprises a semiconductor substrate including first and second regions that have different conductivity types from each other; an isolation region extending continuously over the first and second regions and having a shallow trench covered by a field insulator; first and second active regions placed in respective first and second regions and being each surrounded by the isolation region; a gate electrode disposed in a lower portion of a gate groove that extends continuously from the first active region to the second active region via the isolation region, the gate groove being shallower than the shallow trench; a cap insulating film disposed in an upper portion of the gate groove so as to cover an upper surface of the gate electrode; first and second transistors placed in respective first and second active regions and sharing the gate electrode; and a logic circuit including the first and second transistors connected in series.

Abstract: A semiconductor manufacturing process is disclosed that may form a contact structure with a tungsten plug. A contact structure hole may be adequately filled with tungsten, while avoiding plug loss, increased resistance and/or trenching, that can result from conventional approaches. According to one particular embodiment, a titanium film (003) may be deposited with an anisotropic sputtering method, such as an ion metal plasma method, or the like. A titanium film (003) may have a thickness outside a contact hole (020) that is 100 nm or more. However, due to anisotropic sputtering, a titanium film (003) within a contact hole (020) may be thinner than outside the contact hole (020). A contact hole (020) may then be filled with a tungsten film (005). A tungsten film (005) and titanium film (003) may then be etched back leaving a tungsten plug having shape with an upwardly projecting portion.

Abstract: The present invention provides a manufacturing method of a semiconductor device including the steps of: forming a silicon nitride film on a semiconductor substrate and forming a CVD silicon oxide film on the silicon nitride film, patterning the silicon nitride film and the CVD silicon oxide film using a resist mask, forming a trench by etching the semiconductor substrate by using the patterned silicon nitride film and the patterned CVD silicon oxide film as a mask after releasing the resist mask, and embedding an insulating material into the trench and flattening the embedded insulating material using the silicon nitride film as a stopper, in which the manufacturing method includes a step of annealing the semiconductor substrate after the step of forming the CVD silicon oxide film and before the step of etching the semiconductor substrate.

Abstract: A semiconductor manufacturing process is disclosed that may form a contact structure with a tungsten plug. A contact structure hole may be adequately filled with tungsten, while avoiding plug loss, increased resistance and/or trenching, that can result from conventional approaches. According to one particular embodiment, a titanium film (003) may be deposited with an anisotropic sputtering method, such as an ion metal plasma method, or the like. A titanium film (003) may have a thickness outside a contact hole (020) that is 100 nm or more. However, due to anisotropic sputtering, a titanium film (003) within a contact hole (020) may be thinner than outside the contact hole (020). A contact hole (020) may then be filled with a tungsten film (005). A tungsten film (005) and titanium film (003) may then be etched back leaving a tungsten plug having shape with an upwardly projecting portion.

Abstract: A method of manufacturing a semiconductor device having transistors with lightly doped diffusion regions (LDD) and self-aligned contacts to a reduced inter-gate spaces is disclosed. According to one embodiment, a method may include forming a gate and top insulating layer (004 and 005) on a semiconductor substrate (001). LDD regions (007) may be formed in a first area (Rpc) and source/drain regions (011) may be formed in a second area (Rmc). An etch stop layer (012), which may comprise silicon nitride, can then be formed. Sidewalls (006), which may comprise silicon dioxide, may be formed on gate layer (004) in a first area (Rpc), while inter-gate spaces in the second area (Rmc) may be filled with a sidewall layer. Source/drain regions (008) may then be formed in a first area (Rpc). A heat treatment can be applied that can restore etch resistance properties of the etch stop layer (012) which can be degraded when source/drain regions (008) are formed.

Abstract: A semiconductor device includes a polysilicon film formed directly or indirectly on a semiconductor substrate, and a refractory metal silicide film formed on the polysilicon film. The refractory metal silicide film comprises grains of refractory metal silicide. At least a portion of the grains has a maximum grain diameter equal to or larger than at least one of a film thickness of the refractory metal silicide film and a film width of the refractory metal silicide film.

Abstract: A semiconductor device includes a polysilicon film formed directly or indirectly on a semiconductor substrate, and a refractory metal silicide film formed on the polysilicon film. The refractory metal silicide film comprises grains of refractory metal silicide. At least a portion of the grains has a maximum grain diameter equal to or larger than at least one of a film thickness of the refractory metal silicide film and a film width of the refractory metal silicide film.

Abstract: The semiconductor device disclosed has semiconductor patterns as elements constituting a semiconductor device on a semiconductor substrate. The semiconductor patterns are formed respectively on a first region and a second region on the semiconductor substrate. Between the first region and the second region, there is a stepped portion which is set such that a value S of the step is S=m.lambda./2n wherein .lambda. is a wavelength of the photosensitive illuminating light used in a photolithography process for patterning a photoresist film, m is a positive integer, and n is a refractive index of the photoresist film. The provision of the stepped portion enables the formation of semiconductor element patterns of fine sizes with controllability thereof.

Abstract: The semiconductor device disclosed has semiconductor patterns as elements constituting a semiconductor device on a semiconductor substrate. The semiconductor patterns are formed respectively on a first region and a second region on the semiconductor substrate. Between the first region and the second region, there is a stepped portion which is set such that a value S of the step is S=m.lambda./2n wherein .lambda. is a wavelength of the photosensitive illuminating light used in a photolithography process for patterning a photoresist film, m is a positive integer, and n is a refractive index of the photoresist film. The provision of the stepped portion enables the formation of semiconductor element patterns of fine sizes with controllability thereof.

Abstract: The invention provides a method of fabricating a semiconductor device, including the steps of forming a plurality of active regions on a semiconductor substrate, covering a first active region with mask layers including a first mask layer and a second mask layer deposited on the first mask layer, implanting first electrically conductive type impurities into a second active region with the mask layers acting as a mask, removing the second mask layer, and implanting second electrically conductive type impurities into the first and second active regions. The method makes it possible to form a retrograde-distributed tripe well with less number of masks and less number of ion implantation than conventional methods.

Abstract: In a semiconductor device that includes a first level conductor layer, a second level conductor layer, and a third level conductor layer, the second level conductor layer being positioned at a level between the first and third level conductor layers, a contact hole for electrically connecting the first and third conductor layers is formed in a self-aligned manner, by utilizing an insulating layer which is formed to cover the second level conductor layer in such a manner that the insulator layer surrounds or confines an area where the contact hole is to be formed.

Abstract: A semiconductor device having a superior step coverage of a layer formed inside or near a contact-hole is provided. An intermediate conductive layer is formed through an insulating layer on a lower conductive layer on a semiconductor substrate, and first, second and third inter-layer insulating layers are formed on the intermediate conductive layer. The third inter-layer insulating layer is selectively removed by an isotropic wet etching method thereby to form a through-hole extended to the second inter-layer insulating layer and having a large opening area. In performing this, the second inter-layer insulating layer acts to restrict the removal of the third inter-layer insulating layer in the thickness direction. Next, the first and second inter-layer insulating layers are selectively removed by an anisotropic dry etching method thereby to form a through-hole having a small opening area. The through-hole having a large opening area and the through-hole having a small opening area form a contact-hole.