Patents by Inventor Miguel A. Jimarez

Miguel A. Jimarez has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7353590
    Abstract: A method of forming a printed circuit card with a metal power plane layer between two photoimageable dielectric layers is provided. Photoformed metal filled vias and plated through holes are in the photopatternable material, and signal circuitry is on the surfaces of each of the dielectric materials connected to the vias and plated through holes. A border may be around the card including a metal layer terminating in from the edge of one of the dielectric layers. Copper foil with clearance holes is provided. First and second layers of photoimageable curable dielectric material are on opposite sides of the copper. Patterns are developed on the first and second layers of the photoimageable material to reveal the metal layer through vias. Through holes are developed where holes were patterned in both dielectric layers. The surfaces of the photoimageable material, vias and through holes are metallized by copper plating, preferably using photoresist.
    Type: Grant
    Filed: September 12, 2005
    Date of Patent: April 8, 2008
    Assignee: International Business Machines Corporation
    Inventors: Kenneth Fallon, Miguel A. Jimarez, Ross W. Keesler, John M. Lauffer, Roy H. Magnuson, Voya R. Markovich, Irv Memis, Jim P. Paoletti, Marybeth Perrino, John A. Welsh, William E. Wilson
  • Patent number: 7328506
    Abstract: A method for forming a plated microvia interconnect. An external dielectric layer (EDL) is mounted on a surface of the substrate and is in direct mechanical contact with a conductive element included in the surface. An opening formed in the EDL exposes the conductive element and creates a microvia in the EDL. A sidewall and bottom wall surface of the microvia is treated to promote copper adhesion to the sidewall and bottom wall surfaces. The sidewall and bottom wall surfaces are plated to form a layer of copper thereon. The layer of copper is in direct mechanical and electrical contact with the conductive element. A wet solder paste deposited on the layer of copper overfills a remaining portion of the microvia. The solder paste is reflowed to form a solder bump in and over the remaining portion of the microvia to form the plated microvia interconnect.
    Type: Grant
    Filed: October 25, 2002
    Date of Patent: February 12, 2008
    Assignee: International Business Machines Corporation
    Inventors: Miguel A. Jimarez, Ross W. Keesler, Voya R. Markovich, Rajinder S. Rai, Cheryl L. Tytran-Palomaki
  • Patent number: 7278207
    Abstract: An electronic package and method of making the electronic package is provided. A layer of dielectric material is positioned on a first surface of a substrate which includes a plurality of conductive contacts. At least one through hole is formed in the layer of dielectric material in alignment with at least one of the plurality of conductive contacts. A conductive material is positioned in the at least one through hole substantially filling the through hole. At least one conductive member is positioned on the conductive material in the through hole and in electrical contact with the conductive material. The electronic package improves field operating life of an assembly which includes a semiconductor chip attached to a second surface of the substrate and a printed wiring board attached to the conductive members.
    Type: Grant
    Filed: July 15, 2005
    Date of Patent: October 9, 2007
    Assignee: International Business Machines Corporation
    Inventors: Lisa J. Jimarez, Miguel A. Jimarez, Voya R. Markovich, Cynthia S. Milkovich, Charles H. Perry, Brenda L. Peterson
  • Patent number: 6989607
    Abstract: A method and structure to electrically couple a semiconductor device to a substrate that is divided into a plurality of segments. Alternatively, a semiconductor device may be divided into a plurality of segments and the plurality of segments are electrically coupled to a single substrate.
    Type: Grant
    Filed: July 29, 2003
    Date of Patent: January 24, 2006
    Assignee: International Business Machines Corporation
    Inventors: Krishna Darbha, Miguel A. Jimarez, Matthew M. Reiss, Sanjeev B. Sathe, Charles G. Woychik
  • Patent number: 6986198
    Abstract: A method of forming a printed circuit card with a metal power plane layer between two photoimageable dielectric layers is provided. Photoformed metal filled vias plated through holes are in the photopatternable material, and signal circuitry is on the surfaces of each of the dielectric materials connected to the vias and plated through holes. A border may be around the card including a metal layer termination in from the edge of one of the dielectric layers. Copper foil with clearance holes is provided. First and second layers of photoimageable curable dielectric material are on opposite sides of the copper. Patterns are developed on the first and second layers of the photoimageable material to reveal the metal layer through vias. Through holes are developed where holes were patterned in both dielectric layers. The surfaces of the photoimageable material, vias and through holes are metallized by copper plating, preferably using photoresist.
    Type: Grant
    Filed: December 22, 2003
    Date of Patent: January 17, 2006
    Assignee: International Business Machines Corporation
    Inventors: Kenneth Fallon, Miguel A. Jimarez, Ross W. Keesler, John M. Lauffer, Roy H. Magnuson, Voya R. Markovich, Irv Memis, Jim P. Paoletti, Marybeth Perrino, John A. Welsh, William E. Wilson
  • Patent number: 6961995
    Abstract: An electronic package and method of making the electronic package is provided. A layer of dielectric material is positioned on a first surface of a substrate which includes a plurality of conductive contacts. At least one through hole is formed in the layer of dielectric material in alignment with at least one of the plurality of conductive contacts. A conductive material is positioned in the at least one through hole substantially filling the through hole. At least one conductive member is positioned on the conductive material in the through hole and in electrical contact with the conductive material. The electronic package improves field operating life of an assembly which includes a semiconductor chip attached to a second surface of the substrate and a printed wiring board attached to the conductive members.
    Type: Grant
    Filed: September 19, 2002
    Date of Patent: November 8, 2005
    Assignee: International Business Machines Corporation
    Inventors: Lisa J. Jimarez, Miguel A. Jimarez, Voya R. Markovich, Cynthia S. Milkovich, Charles H. Perry, Brenda L. Peterson
  • Patent number: 6955982
    Abstract: An electrical structure, and associated method of fabrication, for reducing thermally induced strain in a structure that couples a first conductive body of a first substrate to a second conductive body of a second substrate (e.g., a chip to a chip carrier; a chip carrier to a circuit card). The melting point of the first conductive body exceeds the melting point of the second conductive body. The second conductive body may include eutectic lead-tin alloy, while the first conductive body may include non-eutectic lead-tin alloy. A portion of the first conductive body is coated with, or volumetrically surrounded by, a material that is nonsolderable and nonconductive. The first and second conductive bodies are coupled mechanically and electrically by surface adhesion at an uncoated portion of the first conductive body, by application of a temperature that lies between the melting points of the first and second conductive bodies.
    Type: Grant
    Filed: November 18, 2003
    Date of Patent: October 18, 2005
    Assignee: International Business Machines Corporation
    Inventors: Miguel A. Jimarez, Cynthia S. Milkovich, Mark V. Pierson
  • Patent number: 6818972
    Abstract: A method and structure for reducing chip carrier flexing during thermal cycling. A semiconductor chip is coupled to a stiff chip carrier (i.e., a chip carrier having an elastic modulus of at least about 3×105 psi), and there is no stiffener ring on a periphery of the chip carrier. Without the stiffener ring, the chip carrier is able to undergo natural flexing (in contrast with constrained flexing) in response to a temperature change that induces thermal strains due to a mismatch in coefficient of thermal expansion between the chip and the chip carrier. If the temperature at the chip carrier changes from room temperature to a temperature of about −40° C., a maximum thermally induced displacement of a surface of the chip carrier is at least about 25% less if the stiffener ring is absent than if the stiffener ring is present.
    Type: Grant
    Filed: September 30, 2002
    Date of Patent: November 16, 2004
    Assignee: International Business Machines Corporation
    Inventors: Lisa J. Jimarez, Miguel A. Jimarez
  • Publication number: 20040134685
    Abstract: A method of forming a printed circuit board with a metal power plane layer between two photoimageable dielectric layers is provided. Photoformed metal filled vias and plated through holes are in the photopatternable material, and signal circuitry is on the surfaces of each of the dielectric materials connected to the vias and plated through holes. A border may be around the board including a metal layer terminating in from the edge of one of the dielectric layers. Copper foil with clearance holes is provided. First and second layers of photoimageable curable dielectric material are on opposite sides of the copper. Patterns are developed on the first and second layers of the photoimageable material to reveal the metal layer through vias. Through holes are developed where holes were patterned in both dielectric layers. The surfaces of the photoimageable material, vias and through holes are metallized by copper plating, preferably using photoresist.
    Type: Application
    Filed: December 22, 2003
    Publication date: July 15, 2004
    Applicant: International Business Machines Corporation
    Inventors: Kenneth Fallon, Miguel A. Jimarez, Ross W. Keesler, John M. Lauffer, Roy H. Magnuson, Voya R. Markovich, Irv Memis, Jim P. Paoletti, Marybeth Perrino, John A. Welsh, William E. Wilson
  • Patent number: 6757967
    Abstract: A chip mounting assembly is provided which includes a dielectric substrate having at least one integrated circuit (I/C) chip mounted thereon. An electrically conductive cover plate is in contact with all the chips with an electrically non-conducting thermally conducting adhesive. A stiffener member is provided which is mounted ante substrate and laterally spaced from the integrated circuit chip. At least one electrically conductive ground pad is formed an the substrate. The stiffener member has at least one through opening therein and electrically conductive adhesive extending through each opening and contacting the cover plate and each ground pad. The invention also provides a method of forming such an I/C chip assembly.
    Type: Grant
    Filed: April 9, 2002
    Date of Patent: July 6, 2004
    Assignee: International Business Machines Corporation
    Inventors: Lisa J. Jimarez, Miguel A. Jimarez
  • Patent number: 6756680
    Abstract: An electrical structure, and associated method of fabrication, for reducing thermally induced strain in a structure that couples a first conductive body of a first substrate to a second conductive body of a second substrate (e.g., a chip to a chip carrier; a chip carrier to a circuit card). The melting point of the first conductive body exceeds the melting point of the second conductive body. The second conductive body may include eutectic lead-tin alloy, while the first conductive body may include non-eutectic lead-tin alloy. A portion of the first conductive body is coated with, or volumetrically surrounded by, a material that is nonsolderable and nonconductive. The first and second conductive bodies are coupled mechanically and electrically by surface adhesion at an uncoated portion of the first conductive body, by application of a temperature that lies between the melting points of the first and second conductive bodies.
    Type: Grant
    Filed: February 12, 2001
    Date of Patent: June 29, 2004
    Assignee: International Business Machines Corporation
    Inventors: Miguel A. Jimarez, Cynthia S. Milkovich, Mark V. Pierson
  • Patent number: 6750405
    Abstract: A method of forming a printed circuit board or circuit card is provided with a metal layer which serves as a power plane sandwiched between a pair of photoimageable dielectric layers. Photoformed metal filled vias and photoformed plated through holes are in the photopatternable material, and signal circuitry is on the surfaces of each of the dielectric materials and connected to the vias and plated through holes. A border may be around the board or card including a metal layer terminating in from the edge of one of the dielectric layers. A copper foil is provided with clearance holes. First and second layers of photoimageable curable dielectric material is disposed on opposite sides of the copper which are photoimageable material. The patterns are developed on the first and second layers of the photoimageable material to reveal the metal layer through vias. At the clearance holes in the copper, through holes are developed where holes were patterned in both dielectric layers.
    Type: Grant
    Filed: October 17, 2000
    Date of Patent: June 15, 2004
    Assignee: International Business Machines Corporation
    Inventors: Kenneth Fallon, Miguel A. Jimarez, Ross W. Keesler, John M. Lauffer, Roy H. Magnuson, Voya R. Markovich, Irv Memis, Jim P. Paoletti, Marybeth Perrino, John A. Welsh, William E. Wilson
  • Publication number: 20040094842
    Abstract: An electrical structure, and associated method of fabrication, for reducing thermally induced strain in a structure that couples a first conductive body of a first substrate to a second conductive body of a second substrate (e.g., a chip to a chip carrier; a chip carrier to a circuit card). The melting point of the first conductive body exceeds the melting point of the second conductive body. The second conductive body may include eutectic lead-tin alloy, while the first conductive body may include non-eutectic lead-tin alloy. A portion of the first conductive body is coated with, or volumetrically surrounded by, a material that is nonsolderable and nonconductive. The first and second conductive bodies are coupled mechanically and electrically by surface adhesion at an uncoated portion of the first conductive body, by application of a temperature that lies between the melting points of the first and second conductive bodies.
    Type: Application
    Filed: November 18, 2003
    Publication date: May 20, 2004
    Inventors: Miguel A. Jimarez, Cynthia S. Milkovich, Mark V. Pierson
  • Publication number: 20040021205
    Abstract: A method and structure to electrically couple a semiconductor device to a substrate that is divided into a plurality of segments. Alternatively, a semiconductor device may be divided into a plurality of segments and the plurality of segments are electrically coupled to a single substrate.
    Type: Application
    Filed: July 29, 2003
    Publication date: February 5, 2004
    Inventors: Krishna Darbha, Miguel A. Jimarez, Matthew M. Reiss, Sanjeev B. Sathe, Charles G. Woychik
  • Patent number: 6639302
    Abstract: A method and structure to electrically couple a semiconductor device to a substrate that is divided into a plurality of segments. Alternatively, a semiconductor device may be divided into a plurality of segments and the plurality of segments are electrically coupled to a single substrate.
    Type: Grant
    Filed: March 20, 2002
    Date of Patent: October 28, 2003
    Assignee: International Business Machines Corporation
    Inventors: Krishna Darbha, Miguel A. Jimarez, Matthew M. Reiss, Sanjeev B. Sathe, Charles G. Woychik
  • Publication number: 20030178649
    Abstract: A method and structure to electrically couple a semiconductor device to a substrate that is divided into a plurality of segments. Alternatively, a semiconductor device may be divided into a plurality of segments and the plurality of segments are electrically coupled to a single substrate.
    Type: Application
    Filed: March 20, 2002
    Publication date: September 25, 2003
    Applicant: International Business Machines Corporation
    Inventors: Krishna Darbha, Miguel A. Jimarez, Matthew M. Reiss, Sanjeev B. Sathe, Charles G. Woychik
  • Patent number: 6583517
    Abstract: A method and structure to electrically and mechanically join a first a first electrically conductive pad on a first substrate to a second electrically conductive pad on a second substrate using a solder joint that includes a low-melt solder alloy composition. The second electrically conductive pad has a geometry that compels a gap size of a gap between the first substrate and the second substrate to exceed a distance between the first substrate and a surface of the second pad.
    Type: Grant
    Filed: April 9, 2002
    Date of Patent: June 24, 2003
    Assignee: International Business Machines Corporation
    Inventor: Miguel A. Jimarez
  • Publication number: 20030102158
    Abstract: A chip carrier structure and method for forming the same having a receptor pad formed therein. The structure comprises a circuitized substrate having a conductive element on the surface, an External Dielectric Layer mounted on the circuitized substrate with an opening positioned above the conductive element to form a microvia. The walls of the microvia are first treated to enhance copper adhesion and then are electroplated to provide a receptor pad. Finally, a solder paste is deposited within the microvia to create a solder deposit or bump.
    Type: Application
    Filed: October 25, 2002
    Publication date: June 5, 2003
    Inventors: Miguel A. Jimarez, Ross W. Keesler, Voya R. Markovich, Rajinder S. Rai, Cheryl L. Tytran-Palomaki
  • Patent number: 6558981
    Abstract: An encapsulated semiconductor chip module. The chip module has the overlying encapsulant adhered directly and integrally to bare portions of the substrate to which the chip is mounted. This configuration enhances the adhesion and inhibits unintended delamination of the encapsulant from the balance of the module. The module is made by patterning anchor openings into the solder mask. The anchor openings expose corresponding portions of the substrate. It is important to locate the anchor openings over parts of the substrate that do not have circuitry on them, that is, on bare portions, so as to avoid corrosion or contamination of the circuit connections.
    Type: Grant
    Filed: May 3, 2001
    Date of Patent: May 6, 2003
    Assignee: International Business Machines Corporation
    Inventors: Miguel A. Jimarez, Marybeth Perrino, Son K. Tran, Tien Y. Wu
  • Patent number: 6528179
    Abstract: A method and structure for reducing chip carrier flexing during thermal cycling. A semiconductor chip is coupled to a stiff chip carrier (i.e., a chip carrier having an elastic modulus of at least about 3×105 psi), and there is no stiffener ring on a periphery of the chip carrier. Without the stiffener ring, the chip carrier is able to undergo natural flexing (in contrast with constrained flexing) in response to a temperature change that induces thermal strains due to a mismatch in coefficient of thermal expansion between the chip and the chip carrier. If the temperature at the chip carrier changes from room temperature to a temperature of about −40° C., a maximum thermally induced displacement of a surface of the chip carrier is at least about 25% less if the stiffener ring is absent than if the stiffener ring is present.
    Type: Grant
    Filed: October 19, 2000
    Date of Patent: March 4, 2003
    Assignee: International Business Machines Corporation
    Inventors: Lisa J. Jimarez, Miguel A. Jimarez