Abstract: Method of analyzing noise sensitivity of integrated circuits having at least one memory storage device and a noise sensitivity analyzer. In one embodiment, the noise sensitivity analyzer includes a circuit reservoir, a circuit parser and a circuit evaluator. The circuit reservoir is configured to receive and store a model of a circuit having at least one memory storage device to be analyzed. The circuit parser is configured to identify nodes of the model. The circuit evaluator is configured to apply a large test current to each of the nodes for multiple circuit states of the at least one memory storage device and determine which of the nodes are sensitive nodes.

Abstract: A D flip-flop (DFF), a method of operating a DFF, a latch and a library of standard logic elements including standard logic elements corresponding to a DFF and a latch. In one embodiment, the DFF has a data input and a data output and includes: (1) a master stage passgate coupled to the data input, (2) a master stage coupled to the master stage passgate and having a hysteresis inverter with feedback transistors of opposite conductivity, (3) a slave stage passgate coupled to the master stage and (4) a slave stage coupled between the slave stage passgate and the data output and having a hysteresis inverter with feedback transistors of opposite conductivity.

Abstract: Method of analyzing noise sensitivity of integrated circuits having at least one memory storage device and a noise sensitivity analyzer. In one embodiment, the noise sensitivity analyzer includes: (1) a circuit reservoir configured to receive and store a model of a circuit having at least one memory storage device to be analyzed, (2) a circuit parser configured to identify nodes of the model and (3) a circuit evaluator configured to apply a large test current to each of the nodes for multiple circuit states of the at least one memory storage device and determine which of the nodes are sensitive nodes.

Abstract: An apparatus for memory error control coding comprising a first circuit and a second circuit. The first circuit may be configured to generate a multi-bit digital syndrome signal in response to a read data signal and a read parity signal. The second circuit may be configured to (i) detect an error when the bits of the syndrome signal are not all the same state and (ii) generate an error location signal in response the syndrome signal. The error location signal may be generated in response to fewer than all of the bits of the syndrome signal.