Patents by Inventor Miguel Comparan
Miguel Comparan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220344563Abstract: Embodiments of the present disclosure include techniques for interfacing with superconducting circuits and systems. In one embodiment, the present disclosure includes interface circuitry, including driver circuits and/or receiver circuits to send/receive signals with a superconducting circuit. In another embodiment, the present disclosure includes superconducting circuits and techniques for generating a trigger signal from and external clock that is based on a superconducting resonator. In yet another embodiment, the present disclosure includes superconducting data capture circuits that may be used to couple external data to and/or from superconducting logic.Type: ApplicationFiled: April 27, 2021Publication date: October 27, 2022Inventors: Miguel COMPARAN, Adam James MUFF, Indranil SEN, Paul D BERNDT
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Patent number: 11218139Abstract: Ring packet built-in self-test (PBIST) circuitry configured to detect errors in wires connecting a ring of superconducting chips includes circuitry configured to make the PBIST immune to interchip latency and still allow the PBIST to test a stop-to-stop connection. By making a PBIST independent of latency, an entire ring can be characterized for latency and for its bit-error rate prior to running any functional test. Such systems and associated methods can be scaled to larger platforms having any number of ring stops. The PBIST circuitry can function as either transmitter or receiver, or both, to test an entire ring. The PBIST can also be used to tune clocks in the ring to achieve the lowest overall bit error rate (BER) in the ring.Type: GrantFiled: May 14, 2020Date of Patent: January 4, 2022Assignee: NORTHROP GRUMMAN SYSTEMS CORPORATIONInventors: Clint Wayne Mumford, Kshitiz Saxena, Miguel Comparan, Adam Muff, Oscar Rosell
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Publication number: 20210359672Abstract: Ring packet built-in self-test (PBIST) circuitry configured to detect errors in wires connecting a ring of superconducting chips includes circuitry configured to make the PBIST immune to interchip latency and still allow the PBIST to test a stop-to-stop connection. By making a PBIST independent of latency, an entire ring can be characterized for latency and for its bit-error rate prior to running any functional test. Such systems and associated methods can be scaled to larger platforms having any number of ring stops. The PBIST circuitry can function as either transmitter or receiver, or both, to test an entire ring. The PBIST can also be used to tune clocks in the ring to achieve the lowest overall bit error rate (BER) in the ring.Type: ApplicationFiled: May 14, 2020Publication date: November 18, 2021Applicant: NORTHROP GRUMMAN SYSTEMS CORPORATIONInventors: CLINT WAYNE MUMFORD, KSHITIZ SAXENA, MIGUEL COMPARAN, ADAM MUFF, OSCAR ROSELL
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Patent number: 10831504Abstract: A method and circuit arrangement provide support for a hybrid pipeline that dynamically switches between out-of-order and in-order modes. The hybrid pipeline may selectively execute instructions from at least one instruction stream that require the high performance capabilities provided by out-of-order processing in the out-of-order mode. The hybrid pipeline may also execute instructions that have strict power requirements in the in-order mode where the in-order mode conserves more power compared to the out-of-order mode. Each stage in the hybrid pipeline may be activated and fully functional when the hybrid pipeline is in the out-of-order mode. However, stages in the hybrid pipeline not used for the in-order mode may be deactivated and bypassed by the instructions when the hybrid pipeline dynamically switches from the out-of-order mode to the in-order mode. The deactivated stages may then be reactivated when the hybrid pipeline dynamically switches from the in-order mode to the out-of-order mode.Type: GrantFiled: October 2, 2018Date of Patent: November 10, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Miguel Comparan, Andrew D. Hilton, Hans M. Jacobson, Brian M. Rogers, Robert A. Shearer, Ken V. Vu, Alfred T. Watson, III
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Patent number: 10672368Abstract: Systems and methods are disclosed herein for providing improved cache structures and methods that are optimally sized to support a predetermined range of late stage adjustments and in which image data is intelligently read out of DRAM and cached in such a way as to eliminate re-fetching of input image data from DRAM and minimize DRAM bandwidth and power. The systems and methods can also be adapted to work with compressed image data and multiple LSR processing engines.Type: GrantFiled: February 14, 2019Date of Patent: June 2, 2020Assignee: MICROSOFT TECHNOLOGY LICENSING, LLCInventors: Ryan Scott Haraden, Tolga Ozguner, Adam James Muff, Jeffrey Powers Bradford, Christopher Jon Johnson, Gene Leung, Miguel Comparan
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Patent number: 10514753Abstract: Optimizations are provided for late stage reprojection processing for a multi-layered scene. A multi-layered scene is generated. Late stage reprojection processing is applied to a first layer and different late stage reprojection processing is applied to a second layer. The late stage reprojection processing that is applied to the second layer includes one or more transformations that are applied to the second layer. After the late stage reprojection processing on the various layers is complete, a unified layer is created by compositing the layers together. Then, the render the unified layer is rendered.Type: GrantFiled: March 27, 2017Date of Patent: December 24, 2019Assignee: Microsoft Technology Licensing, LLCInventors: Ryan Scott Haraden, Jeffrey Powers Bradford, Miguel Comparan, Adam James Muff, Gene Leung, Tolga Ozguner
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Patent number: 10410349Abstract: Optimizations are provided for late stage reprojection processing for a multi-layered scene. A scene is generated, which is based on a predicted pose of a portion of a computer system. A sub-region is identified within one of the layers and is isolated from the other regions in the scene. Thereafter, late stage reprojection processing is applied to that sub-region selectively/differently than other regions in the scene that do not undergo the same late state reprojection processing.Type: GrantFiled: March 27, 2017Date of Patent: September 10, 2019Assignee: Microsoft Technology Licensing, LLCInventors: Ryan Scott Haraden, Jeffrey Powers Bradford, Miguel Comparan, Adam James Muff, Gene Leung, Tolga Ozguner
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Patent number: 10403029Abstract: Systems and methods for multistage post-rendering image transformation are provided. The system may include a transform generation module arranged to dynamically generate an image transformation. The system may include a transform data generation module arranged to generate first and second transformation data by applying the generated image transformation for first and second sampling positions and storing the transformation data in a memory. The system may include a first image transformation stage that selects the first and second transformation data for a destination image position and calculates an estimated source image position based on the selected first and second transformation data.Type: GrantFiled: May 3, 2017Date of Patent: September 3, 2019Assignee: MICROSOFT TECHNOLOGY LICENSING, LLCInventors: Tolga Ozguner, Miguel Comparan, Ryan Scott Haraden, Jeffrey Powers Bradford
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Patent number: 10360832Abstract: Techniques for post-rendering image transformation including outputting an image frame including a plurality of first pixels by sequentially generating and outputting multiple color component fields including a first color component field and a second color component field by applying one or more two-dimensional (2D) image transformations to at least one portion of the plurality of source pixels by first, second, and third image transformation pipelines, to generate transformed pixel color data for the first color component field and the second color component field.Type: GrantFiled: August 14, 2017Date of Patent: July 23, 2019Assignee: MICROSOFT TECHNOLOGY LICENSING, LLCInventors: Tolga Ozguner, Miguel Comparan, Christopher Jon Johnson, Jeffrey Powers Bradford
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Patent number: 10338816Abstract: Techniques for controlling access to a memory are provided. The techniques may include receiving and storing output pixel data in a buffer, providing the stored output pixel data to a display controller, receiving stored output pixel data from the buffer at the display controller, switching to a second operating mode state based at least on an amount of available data in the buffer being less than or equal to a threshold, identifying a portion of the image data stored in a memory device for use in generating output pixel data for an updated image, and, in response to operating in the second operating mode, generating the output pixel data without issuing a memory read command via an interconnect to retrieve the portion of the initial image while operating in the second operating mode, and providing the output pixel data to the buffer.Type: GrantFiled: October 8, 2018Date of Patent: July 2, 2019Assignee: MICROSOFT TECHNOLOGY LICENSING, LLCInventors: Tolga Ozguner, Ishan Jitendra Bhatt, Miguel Comparan, Ryan Scott Haraden, Jeffrey Powers Bradford, Gene Leung
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Publication number: 20190189089Abstract: Systems and methods are disclosed herein for providing improved cache structures and methods that are optimally sized to support a predetermined range of late stage adjustments and in which image data is intelligently read out of DRAM and cached in such a way as to eliminate re-fetching of input image data from DRAM and minimize DRAM bandwidth and power. The systems and methods can also be adapted to work with compressed image data and multiple LSR processing engines.Type: ApplicationFiled: February 14, 2019Publication date: June 20, 2019Inventors: Ryan Scott HARADEN, Tolga OZGUNER, Adam James MUFF, Jeffrey Powers BRADFORD, Christopher Jon JOHNSON, Gene LEUNG, Miguel COMPARAN
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Patent number: 10255891Abstract: Systems and methods are disclosed herein for providing improved cache structures and methods that are optimally sized to support a predetermined range of late stage adjustments and in which image data is intelligently read out of DRAM and cached in such a way as to eliminate re-fetching of input image data from DRAM and minimize DRAM bandwidth and power. The systems and methods can also be adapted to work with compressed image data and multiple LSR processing engines.Type: GrantFiled: April 12, 2017Date of Patent: April 9, 2019Assignee: Microsoft Technology Licensing, LLCInventors: Ryan Scott Haraden, Tolga Ozguner, Adam James Muff, Jeffrey Powers Bradford, Christopher Jon Johnson, Gene Leung, Miguel Comparan
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Patent number: 10241470Abstract: Systems and methods are disclosed herein for providing improved cache structures and methods that are optimally sized to support a predetermined range of late stage adjustments and in which image data is intelligently read out of DRAM and cached in such a way as to eliminate re-fetching of input image data from DRAM and minimize DRAM bandwidth and power. The systems and methods can also be adapted to work with compressed image data.Type: GrantFiled: May 15, 2018Date of Patent: March 26, 2019Assignee: Microsoft Technology Licensing, LLCInventors: Tolga Ozguner, Gene Leung, Jeffrey Powers Bradford, Adam James Muff, Miguel Comparan, Ryan Scott Haraden, Christopher Jon Johnson
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Patent number: 10242654Abstract: Systems and methods are disclosed herein for providing improved cache structures and methods that are optimally sized to support a predetermined range of late stage adjustments and in which image data is intelligently read out of DRAM and cached in such a way as to eliminate re-fetching of input image data from DRAM and minimize DRAM bandwidth and power.Type: GrantFiled: January 25, 2017Date of Patent: March 26, 2019Assignee: Microsoft Technology Licensing, LLCInventors: Tolga Ozguner, Jeffrey Powers Bradford, Miguel Comparan, Gene Leung, Adam James Muff, Ryan Scott Haraden, Christopher Jon Johnson
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Publication number: 20190050149Abstract: Techniques for controlling access to a memory are provided. The techniques may include receiving and storing output pixel data in a buffer, providing the stored output pixel data to a display controller, receiving stored output pixel data from the buffer at the display controller, switching to a second operating mode state based at least on an amount of available data in the buffer being less than or equal to a threshold, identifying a portion of the image data stored in a memory device for use in generating output pixel data for an updated image, and, in response to operating in the second operating mode, generating the output pixel data without issuing a memory read command via an interconnect to retrieve the portion of the initial image while operating in the second operating mode, and providing the output pixel data to the buffer.Type: ApplicationFiled: October 8, 2018Publication date: February 14, 2019Applicant: MICROSOFT TECHNOLOGY LICENSING, LLCInventors: Tolga OZGUNER, Ishan Jitendra BHATT, Miguel COMPARAN, Ryan Scott HARADEN, Jeffrey Powers BRADFORD, Gene LEUNG
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Publication number: 20190051229Abstract: Techniques for post-rendering image transformation including outputting an image frame including a plurality of first pixels by sequentially generating and outputting multiple color component fields including a first color component field and a second color component field by applying one or more two-dimensional (2D) image transformations to at least one portion of the plurality of source pixels by first, second, and third image transformation pipelines, to generate transformed pixel color data for the first color component field and the second color component field.Type: ApplicationFiled: August 14, 2017Publication date: February 14, 2019Applicant: MICROSOFT TECHNOLOGY LICENSING, LLCInventors: Tolga OZGUNER, Miguel COMPARAN, Christopher Jon JOHNSON, Jeffrey Powers BRADFORD
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Publication number: 20190034208Abstract: A method and circuit arrangement provide support for a hybrid pipeline that dynamically switches between out-of-order and in-order modes. The hybrid pipeline may selectively execute instructions from at least one instruction stream that require the high performance capabilities provided by out-of-order processing in the out-of-order mode. The hybrid pipeline may also execute instructions that have strict power requirements in the in-order mode where the in-order mode conserves more power compared to the out-of-order mode. Each stage in the hybrid pipeline may be activated and fully functional when the hybrid pipeline is in the out-of-order mode. However, stages in the hybrid pipeline not used for the in-order mode may be deactivated and bypassed by the instructions when the hybrid pipeline dynamically switches from the out-of-order mode to the in-order mode. The deactivated stages may then be reactivated when the hybrid pipeline dynamically switches from the in-order mode to the out-of-order mode.Type: ApplicationFiled: October 2, 2018Publication date: January 31, 2019Inventors: Miguel Comparan, Andrew D. Hilton, Hans M. Jacobson, Brian M. Rogers, Robert A. Shearer, Ken V. Vu, Alfred T. Watson, III
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Publication number: 20180322688Abstract: Systems and methods for multistage post-rendering image transformation are provided. The system may include a transform generation module arranged to dynamically generate an image transformation. The system may include a transform data generation module arranged to generate first and second transformation data by applying the generated image transformation for first and second sampling positions and storing the transformation data in a memory. The system may include a first image transformation stage that selects the first and second transformation data for a destination image position and calculates an estimated source image position based on the selected first and second transformation data.Type: ApplicationFiled: May 3, 2017Publication date: November 8, 2018Applicant: MICROSOFT TECHNOLOGY LICENSING, LLCInventors: Tolga OZGUNER, Miguel COMPARAN, Ryan Scott HARADEN, Jeffrey Powers BRADFORD
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Patent number: 10114652Abstract: A method and circuit arrangement provide support for a hybrid pipeline that dynamically switches between out-of-order and in-order modes. The hybrid pipeline may selectively execute instructions from at least one instruction stream that require the high performance capabilities provided by out-of-order processing in the out-of-order mode. The hybrid pipeline may also execute instructions that have strict power requirements in the in-order mode where the in-order mode conserves more power compared to the out-of-order mode. Each stage in the hybrid pipeline may be activated and fully functional when the hybrid pipeline is in the out-of-order mode. However, stages in the hybrid pipeline not used for the in-order mode may be deactivated and bypassed by the instructions when the hybrid pipeline dynamically switches from the out-of-order mode to the in-order mode. The deactivated stages may then be reactivated when the hybrid pipeline dynamically switches from the in-order mode to the out-of-order mode.Type: GrantFiled: April 12, 2016Date of Patent: October 30, 2018Assignee: International Business Machines CorporationInventors: Miguel Comparan, Andrew D. Hilton, Hans M. Jacobson, Brian M. Rogers, Robert A. Shearer, Ken V. Vu, Alfred T. Watson, III
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Publication number: 20180301125Abstract: Systems and methods are disclosed herein for providing improved cache structures and methods that are optimally sized to support a predetermined range of late stage adjustments and in which image data is intelligently read out of DRAM and cached in such a way as to eliminate re-fetching of input image data from DRAM and minimize DRAM bandwidth and power. The systems and methods can also be adapted to work with compressed image data and multiple LSR processing engines.Type: ApplicationFiled: April 12, 2017Publication date: October 18, 2018Inventors: Ryan Scott Haraden, Tolga Ozguner, Adam James Muff, Jeffrey Powers Bradford, Christopher Jon Johnson, Gene Leung, Miguel Comparan