Patents by Inventor Miguel Corvacho

Miguel Corvacho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and apparatus to utilize a digital-time-conversion (DTC) based clocking in computing systems
    Patent number: 11327523
    Abstract: A system is provided which comprises: a first circuitry to generate a first clock signal; and a second circuitry to generate a second clock signal such that: a frequency of the second clock signal is varied over a clock pulse of the first clock signal, and an average of the frequency of the second clock signal over the clock pulse of the first clock signal is substantially maintained at a target frequency.
    Type: Grant
    Filed: February 24, 2020
    Date of Patent: May 10, 2022
    Assignee: Intel Corporation
    Inventors: Eyal Fayneh, Elias Nassar, Inbar Falkov, Ramkumar Krithivasan, Vijay K. Vuppaladadium, Miguel A. Corvacho Hernandez, Samer Nassar, Yair Talker
  • METHOD AND APPARATUS TO UTILIZE A DIGITAL-TIME-CONVERSION (DTC) BASED CLOCKING IN COMPUTING SYSTEMS
    Publication number: 20200301465
    Abstract: A system is provided which comprises: a first circuitry to generate a first clock signal; and a second circuitry to generate a second clock signal such that: a frequency of the second clock signal is varied over a clock pulse of the first clock signal, and an average of the frequency of the second clock signal over the clock pulse of the first clock signal is substantially maintained at a target frequency.
    Type: Application
    Filed: February 24, 2020
    Publication date: September 24, 2020
    Applicant: Intel Corporation
    Inventors: Eyal FAYNEH, Elias NASSAR, Inbar FALKOV, Ramkumar KRITHIVASAN, Vijay K. VUPPALADADIUM, Miguel A. CORVACHO HERNANDEZ, Samer NASSAR, Yair TALKER
  • Method and apparatus to utilize a digital-time-conversion (DTC) based clocking in computing systems
    Patent number: 10571953
    Abstract: A system is provided which comprises: a first circuitry to generate a first clock signal; and a second circuitry to generate a second clock signal such that: a frequency of the second clock signal is varied over a clock pulse of the first clock signal, and an average of the frequency of the second clock signal over the clock pulse of the first clock signal is substantially maintained at a target frequency.
    Type: Grant
    Filed: July 5, 2017
    Date of Patent: February 25, 2020
    Assignee: Intel Corporation
    Inventors: Eyal Fayneh, Elias Nassar, Inbar Falkov, Ramkumar Krithivasan, Vijay K. Vuppaladadium, Miguel A. Corvacho Hernandez, Samer Nasser, Yair Talker
  • METHOD AND APPARATUS TO UTILIZE A DIGITAL-TIME-CONVERSION (DTC) BASED CLOCKING IN COMPUTING SYSTEMS
    Publication number: 20190011945
    Abstract: A system is provided which comprises: a first circuitry to generate a first clock signal; and a second circuitry to generate a second clock signal such that: a frequency of the second clock signal is varied over a clock pulse of the first clock signal, and an average of the frequency of the second clock signal over the clock pulse of the first clock signal is substantially maintained at a target frequency.
    Type: Application
    Filed: July 5, 2017
    Publication date: January 10, 2019
    Applicant: Intel Corporation
    Inventors: Eyal FAYNEH, Elias NASSAR, Inbar FALKOV, Ramkumar KRITHIVASAN, Vijay K. VUPPALADADIUM, Miguel A. CORVACHO HERNANDEZ, Samer NASSER, Yair TALKER
  • Circuits and methods for alignment of signals in integrated circuits
    Patent number: 6891417
    Abstract: Circuits and methods align an internal signal with an external signal. A phase lock loop network receives the external signal to generate phase lock loop signals. A programmable ratio decoder provides a code. An alignment unit generates the internal signal based on at least one of the phase lock loop signals. The alignment unit aligns internal signal with the external signal based on the code.
    Type: Grant
    Filed: July 2, 2003
    Date of Patent: May 10, 2005
    Assignee: Intel Corporation
    Inventors: Tanveer R Khondker, Vijay Vuppaladadium, Inder Sodhi, Venkatesh Prasanna, Kedar Mangrulkar, Miguel Corvacho, Nakul Arora
  • CIRCUITS AND METHODS FOR ALIGNMENT OF SIGNALS IN INTEGRATED CIRCUITS
    Publication number: 20050001664
    Abstract: Circuits and methods align an internal signal with an external signal. A phase lock loop network receives the external signal to generate phase lock loop signals. A programmable ratio decoder provides a code. An alignment unit generates the internal signal based on at least one of the phase lock loop signals. The alignment unit aligns internal signal with the external signal based on the code.
    Type: Application
    Filed: July 2, 2003
    Publication date: January 6, 2005
    Inventors: Tanveer Khondker, Vijay Vuppaladadium, Inder Sodhi, Venkatesh Prasanna, Kedar Mangrulkar, Miguel Corvacho, Nakul Arora