Abstract: A DPRAM is placed in the RF path before the digital to analog converter, to provide dynamic path gain compensation to the digital signal prior to conversion to an analog signal. The DPRAM stores corrections to the signal to compensate for amplitude losses in the signal arising from heat and non-linearities. The DPRAM has two sets of identical addresses. A logic switch, alternately directs an input signal to one of the two sets of addresses. Pre-calculated signal values which compensate for path gain are stored in one of the two sets of addresses in the DPRAM. The signal Input to the DPRAM is directed to the other block. The value of the signal input to the DPRAM will determine the address to which the new value can be found. It is this new value which is actually input to the DAC and from which an analog signal is created.

Abstract: Disclosed is an interface and method for data transmission between digital and radio frequency (RF) components of a base station. The interface and method involves transmitting transmit or receive data over a first set of time slots and transmitting various uplink or downlink low rate static/control signals over a second set of time slots. The transmit data includes in-phase transmit data bits and quadrature phase transmit bits, and the receive data includes in-phase transmit data bits and quadrature phase transmit bits received over a diversity antenna system.

Abstract: A method and circuit for performing a wired-or function in a differential transmission environment are disclosed. The wired-or function is realized by enabling the differential driver portion of the differential transceiver when the signaling path is to be driven with a logical true signal and disabling the differential driver portion when a logical false signal is to transmitted to the signaling path. In a preferred embodiment, a 1394 backplane node (a node is a single connection to the bus which may or may not be shared by multiple devices) is implemented using commercially available chips including a physical arbiter, a link controller, a differential transceiver, a programmable logic device, and some additional transistors.

Abstract: A processor monitors the real time forward link power utilization in a base station, and a controller regulates the real time forward link power utilization in the base station. The processor and controller operate in a feedback configuration to maintain call quality and prevent damage to the base station. The processor determines real time forward link power utilization on a per frame basis by taking samples at a per chip rate within each frame. The forward link power is then obtained by taking the mean of the samples.

Abstract: An apparatus and method for centralized processing of PIP images from a plurality of digital video sources includes a centralized processing device having a plurality of service drivers for outputting digital video data representing full screen images, and samplers for selectively sampling the data from the service drivers to form reduced screen images. A PIP bus channels the sampled data for access by various users. The sample data is selectively stored in buffers and is output to a display device when triggered by input/output triggers. The triggered output data representing reduced screen images is then combined by a video switch to form picture-in-picture images.