Abstract: An induced pulse diversion circuit (12) senses the presence of pulses in an input signal, particularly &bgr; and &ggr; pulses induced into the photocurrent input to a focal plane readout unit cell (50), and diverts them from a main signal path (14) to a diversion path (16). A pair of gate devices (18,20) control access to the signal and diversion paths, respectively. An inverting amplifier (30) receives the incoming photocurrent and, upon receipt of an induced pulse, produces an output that turns on the diversion path's gate device (20) and turns off the signal path's gate device (18). The invention reduces the occurrence of “toggling” by limiting the negative-going excursions of the inverting amplifier made in response to an induced pulse, so that the amplifier is prevented from being driven into saturation.

Abstract: A background suppression technique uses well-controlled and repeatable charge skimming operations to increase the charge capacities of the integration capacitors of integrated focal plane readout unit cells. A MOSFET (Q1) is connected to an integration capacitor (C.sub.int) from which the quantity of stored charge is to be reduced. During each photocurrent integration period, the MOSFET is driven with a "skimming pulse" (V.sub.sk) to draw charge from the capacitor. The skimming pulse is substantially shorter than an integration period, reducing the amount of noise contributed by the MOSFET's noise mechanisms, and has an amplitude great enough to drive the MOSFET into its strong inversion mode, making the quantity of the removed charge relatively insensitive to variations in MOSFET threshold voltage. The charge skimming pulse is arranged to reduce the charge on the capacitor almost, but not quite, to zero, so that the entire integration period remains utilized.

Abstract: An analog-digital correlator 10 utilizes a plurality of sample and hold cirucits 16-0 to 16-(M-1) to directly store samples of a received analog signal. Bits of a correlation pattern are shifted through stages in a correlation pattern shift register 26. The state of the correlation pattern bits causes the value in the associated sample and hold circuit 16 to either be inverted or noninverted when it is summed with other similarly generated signals from the remaining sample and hold circuits to form the correlation output sum by network 30. The output of network 30 will peak when the bits of the digital correlation pattern signal are shifted to stages in register 26 that are aligned with the sample and hold circuits containing the digitally-impressed code of interest. In the preferred embodiment, a mask shift register 28 is used to selectively disable certain of the sample and hold circuits from affecting the correlation output sum.