Abstract: Aspects of the invention include a circuit having a power header configured to couple to a power supply and to provide an output voltage. A sense circuit is coupled to the power header to receive the output voltage, the sense circuit including a replica voltage circuit coupled to a replica power header circuit and a transistor, the replica voltage circuit being configured to provide a replicated output voltage in accordance with the output voltage, the replica power header circuit being configured to couple to the power supply and the replicated output voltage to generate a replica current, the transistor being configured to deliver the replica current.

Abstract: Aspects of the invention include a circuit having a two-stage amplifier coupled to a transistor array and to a comparator, the transistor array being configured to provide an output to a load, the transistor array including transistors. The circuit includes a controller coupled to the comparator and to the transistor array, the two-stage amplifier being configured to modulate a current density in the transistor array via gate terminals of the transistors, wherein, by using the comparator and the controller, the two-stage amplifier is configured to modulate a number of the transistors that are to couple to the load.

Abstract: Aspects of the invention include a circuit having a power header configured to couple to a power supply and to provide an output voltage. A sense circuit is coupled to the power header to receive the output voltage, the sense circuit including a replica voltage circuit coupled to a replica power header circuit and a transistor, the replica voltage circuit being configured to provide a replicated output voltage in accordance with the output voltage, the replica power header circuit being configured to couple to the power supply and the replicated output voltage to generate a replica current, the transistor being configured to deliver the replica current.

Abstract: Aspects of the invention include a circuit having a two-stage amplifier coupled to a transistor array and to a comparator, the transistor array being configured to provide an output to a load, the transistor array including transistors. The circuit includes a controller coupled to the comparator and to the transistor array, the two-stage amplifier being configured to modulate a current density in the transistor array via gate terminals of the transistors, wherein, by using the comparator and the controller, the two-stage amplifier is configured to modulate a number of the transistors that are to couple to the load.

Abstract: A technique relates to a digital phase locked loop (DPLL) including a digitally controlled oscillator (DCO), the DCO having delay elements and a current fill factor corresponding to a proportion of the delay elements in operation. A voltage regulator controller is operable to obtain a result of a comparison between a predefined fill factor and the current fill factor, the voltage regulator controller being operable to adjust voltage supplied to the DCO based on the result, the predefined fill factor indicating a predetermined proportion of the delay elements to be in operation.

Abstract: An analog multiplexer includes a plurality of voltage-protecting transmission gate circuits to select an input voltage signal among different input signals. Each voltage-protecting transmission gate circuit includes a pass gate pFET interconnected between an input pFET and an output pFET, as well as a parallel pass gate nFET. The pFET includes a first source/drain connected in series with the input pFET. A second source/drain is connected in series with the output pFET. A pFET gate receives a gate select signal that operates the transmission gate circuit in a blocking mode, a first passing mode, or a second passing mode. The nFET includes a first nFET source/drain connected to the input pFET to form a main input terminal that receives the input voltage signal. A second nFET source/drain is connected to the output pFET to form a main output terminal that outputs an output voltage based on the operating mode.

Abstract: An analog multiplexer includes a plurality of voltage-protecting transmission gate circuits to select an input voltage signal among different input signals. Each voltage-protecting transmission gate circuit includes a pass gate pFET interconnected between an input pFET and an output pFET, as well as a parallel pass gate nFET. The pFET includes a first source/drain connected in series with the input pFET. A second source/drain is connected in series with the output pFET. A pFET gate receives a gate select signal that operates the transmission gate circuit in a blocking mode, a first passing mode, or a second passing mode. The nFET includes a first nFET source/drain connected to the input pFET to form a main input terminal that receives the input voltage signal. A second nFET source/drain is connected to the output pFET to form a main output terminal that outputs an output voltage based on the operating mode.