Abstract: A three-dimensional (3D) integrated circuit (IC) includes a first die. The first die includes a 3D stacked capacitor on a first surface of the first die and coupled to a power distribution network (PDN) of the first die. The 3D IC also includes a second die stacked on the first surface of the first die, proximate the 3D stacked capacitor on the first surface of the first die. The 3D IC further includes active circuitry coupled to the 3D stacked capacitor through the PDN of the first die.

Abstract: A three-dimensional (3D) integrated circuit (IC) includes a first die. The first die includes a 3D stacked capacitor on a first surface of the first die and coupled to a power distribution network (PDN) of the first die. The 3D IC also includes a second die stacked on the first surface of the first die, proximate the 3D stacked capacitor on the first surface of the first die. The 3D IC further includes active circuitry coupled to the 3D stacked capacitor through the PDN of the first die.

Abstract: A heterojunction bipolar transistor unit cell may include a compound semiconductor substrate. The heterojunction bipolar transistor unity may also include a base mesa on the compound semiconductor substrate. The base mesa may include a collector region on the compound semiconductor substrate and a base region on the collector region. The heterojunction bipolar transistor unity may further include a single emitter mesa on the base mesa.

Abstract: A heterojunction bipolar transistor unit cell may include a compound semiconductor substrate. The heterojunction bipolar transistor unity may also include a base mesa on the compound semiconductor substrate. The base mesa may include a collector region on the compound semiconductor substrate and a base region on the collector region. The heterojunction bipolar transistor unity may further include a single emitter mesa on the base mesa.

Abstract: Disclosed is a heterojunction bipolar transistor, and method of manufacturing the same, including an emitter having a conductive emitter contact coupled to a first side of the emitter, a first side of a base coupled to a second side of the emitter opposite the first side of the emitter, a collector coupled to the base on a second side of the base opposite the emitter, wherein an area of a junction between the base and the collector is less than or equal to an area of a junction between the base and the emitter, a first conductive base contact coupled to the base, and a conductive collector contact coupled to the collector on the side of the collector opposite the emitter and substantially parallel to the first conductive base contact.

Abstract: A method is disclosed for analyzing a performance metric of an array type electronic circuit under process variability effects. The electronic circuit has an array with a plurality of array elements and an access path being a model of the array type electronic circuit. The model includes building blocks having all hardware to access one array element in the array. Each building block has at least one basic element. In one aspect, the method includes deriving statistics of the access path due to variations in the building blocks under process variability of the basic elements, and deriving statistics of the full array type electronic circuit by combining the results of the statistics of the access path under awareness of the array architecture.