Abstract: A device including at least one processor, and an analog-to-digital (ADC) circuit, wherein the at least one processor is configured to generate an excitation signal and provide the excitation signal to a crystal in a pierce oscillation configuration, wherein after providing the excitation signal, the ADC circuit is configured to obtain as input a signal output from the crystal and convert the signal to a digital output; the at least one processor is configured to compare the digital output of the ADC circuit to a plurality of thresholds and based on the comparisons is further configured to drive the crystal to cause the crystal to operate as a pierce oscillator and to generate a clock signal from at least of one of the comparisons.

Abstract: A calibration circuit, including: a signal generator circuit configured to generate a modulated analog input signal, which is based on a digital input word that is modulated; an Analog-to-Digital Converter (ADC) configured to convert an analog reference signal to a digital calibration word, wherein the analog reference signal is a low-pass-filtered version of the analog input signal generated by the signal generator circuit; and a feedback circuit configured to output the digital input word by adjusting the digital calibration word depending on a digital feedback signal, which is based on a modulated version of the analog reference signal, wherein the signal generator circuit, the ADC, and the feedback circuit are provided on a same chip.

Abstract: In an embodiment, a semiconductor device is disclosed that includes at least one processing device and firmware including a dynamic demodulation engine. The dynamic demodulation engine, when executed by the at least one processing device, is configured to obtain a digital signal waveform, dynamically select a bit detection method based at least in part on a characteristic of the digital signal waveform, perform demodulation of the digital signal waveform using the selected bit detection method and generate decoded packets based at least in part on the demodulation.

Abstract: Systems and methods for demodulating a signal is described. A device can receive a modulated signal that encodes data. The device can sample a voltage of the modulated signal to generate a plurality of samples in digital domain. The device can determine in-phase data and quadrature data of the plurality of samples. The device can determine amplitude data and phase data based on the in-phase data and the quadrature data. The device can decode the amplitude data and phase data into digital symbols that represent the data encoded in the modulated signal.

Abstract: According to an example, an electronic device includes a component, a supply line providing a supply voltage, a transistor with a control input, a linear first control loop, and a non-linear second control loop. The transistor outputs an output voltage to the component depending on a signal applied to the control input. The linear first control loop includes an ADC to convert an analog output voltage level into a digital measurement signal, a controller to generate a digital control signal for the transistor depending on the digital measurement signal, and a DAC to convert the digital control signal into a first analog control signal. The non-linear second control loop is configured to generate a second analog control signal depending on the analog output voltage level. The second analog control signal is superimposed with the first analog control signal and the combined control signals are fed to the control input of the transistor.

Abstract: A device is provided for time measurement of a clock-based signal comprising a sample stage comprising a switching device that is driven by a control signal and a capacitance (Cs), wherein the sample stage is arranged to transform an analog input signal in an analog output signal, the device further comprising an analog-to-digital converter to convert the analog output signal into a digital output signal, wherein the input signal applied to the sample stage is a reference signal and wherein the clock-based signal is applied to the control signal. Also, an according method is suggested.

Abstract: A calibration circuit, including: a signal generator circuit configured to generate a modulated analog input signal, which is based on a digital input word that is modulated; an Analog-to-Digital Converter (ADC) configured to convert an analog reference signal to a digital calibration word, wherein the analog reference signal is a low-pass-filtered version of the analog input signal generated by the signal generator circuit; and a feedback circuit configured to output the digital input word by adjusting the digital calibration word depending on a digital feedback signal, which is based on a modulated version of the analog reference signal, wherein the signal generator circuit, the ADC, and the feedback circuit are provided on a same chip.

Abstract: A calibration circuit, including: a first analog-to-digital converter (ADC) configured to sample a nonlinear reference signal continuously at an equidistant sampling rate to generate a reference sampled signal; a trigger timer configured to generate trigger signals; a second ADC configured to sample a point of each of the nonlinear reference signal and repeated versions of the nonlinear reference signal in response to the respective trigger signals at equidistantly increasing delays, to generate a device-under-test (DUT) sampled voltage; and processing circuitry configured to estimate a differential nonlinearity (DNL) of the DUT sampled signal, estimate a DNL of the reference sampled signal, and compare the estimated DNL of the DUT sampled signal with the estimated DNL of the reference sampled signal, to generate a DNL performance indication signal of the second ADC.

Abstract: According to an example, an electronic device includes a component, a supply line providing a supply voltage, a transistor with a control input, a linear first control loop, and a non-linear second control loop. The transistor outputs an output voltage to the component depending on a signal applied to the control input. The linear first control loop includes an ADC to convert an analog output voltage level into a digital measurement signal, a controller to generate a digital control signal for the transistor depending on the digital measurement signal, and a DAC to convert the digital control signal into a first analog control signal. The non-linear second control loop is configured to generate a second analog control signal depending on the analog output voltage level. The second analog control signal is superimposed with the first analog control signal and the combined control signals are fed to the control input of the transistor.

Abstract: Systems, methods, and circuits are provided for facilitating negative resistance margin testing in an oscillator circuit. An example oscillator circuit includes amplifier circuitry configured to be coupled in parallel with a resonator and variable resistance circuitry configured to, in response to a resistance control signal, adjust a resistance of the oscillator circuit.

Abstract: Systems, methods, and circuits are provided for facilitating negative resistance margin testing in an oscillator circuit. An example oscillator circuit includes amplifier circuitry configured to be coupled in parallel with a resonator and variable resistance circuitry configured to, in response to a resistance control signal, adjust a resistance of the oscillator circuit.

Abstract: A device is provided for time measurement of a clock-based signal comprising a sample stage comprising a switching device that is driven by a control signal and a capacitance (Cs), wherein the sample stage is arranged to transform an analog input signal in an analog output signal, the device further comprising an analog-to-digital converter to convert the analog output signal into a digital output signal, wherein the input signal applied to the sample stage is a reference signal and wherein the clock-based signal is applied to the control signal. Also, an according method is suggested.

Abstract: Processing a resolver signal by a microcontroller includes generating, by a carrier signal generator, a carrier signal for output to a resolver; receiving modulated carrier signals from a resolver via hardware that is external to the microcontroller; integrating, by an integrator, respective integrator input signals which are based on the modulated carrier signals, to generate respective envelope signals, wherein a start of an integration window of the integrator is set with respect to a start of the carrier signal; and determining an angular position sensed by the resolver based on the envelope signals.

Abstract: A DC/DC power converter and a method to convert an input voltage into an output voltage are presented. The power converter may have a first flying capacitor, a second flying capacitor, an inductor, and switching elements. It may control the switching elements such that the switching elements establish a first magnetizing current path from the input node, via the first flying capacitor, via the second flying capacitor, via the inductor, to the output node. The converter may control the switching elements to interrupt said first magnetizing current path after a pre-determined time interval. The converter may control the switching elements such that the switching elements establish a demagnetizing current path from a reference potential via the inductor to the output node. The converter may control the switching elements such that said demagnetizing current path is interrupted when a current through the inductor reaches a pre-determined threshold current value.

Abstract: A DC/DC power converter and a method to convert an input voltage into an output voltage are presented. The power converter may have a first flying capacitor, a second flying capacitor, an inductor, and switching elements. It may control the switching elements such that the switching elements establish a first magnetizing current path from the input node, via the first flying capacitor, via the second flying capacitor, via the inductor, to the output node. The converter may control the switching elements to interrupt said first magnetizing current path after a pre-determined time interval. The converter may control the switching elements such that the switching elements establish a demagnetizing current path from a reference potential via the inductor to the output node. The converter may control the switching elements such that said demagnetizing current path is interrupted when a current through the inductor reaches a pre-determined threshold current value.

Abstract: A digital voltage regulator and a method to regulate an output voltage at an output node based on an input voltage is presented. The regulator has a driver stage with N driver slices, with N>1. Each of the N driver slices can be activated or deactivated individually. A driver slice comprises a current source to provide an output current component to the output node, if the driver slice is activated. Furthermore, the regulator has a control unit to activate a number n of the N driver slices, based on a deviation of a feedback voltage from a reference voltage, where the feedback voltage is dependent on the output voltage.

Abstract: A linear charger circuit and method for providing an output current at an output node is presented. The circuit contains a pass device connected between an input node and the output node, first and second replica devices connected in parallel to the pass device, with their control terminals coupled to a control terminal of the pass device. The first replica device is coupled to a first circuit path for determining whether current output by the linear charger circuit shall be terminated. The second replica device is coupled to a second circuit path for providing feedback for controlling the pass device, a control circuit coupled to the second circuit path for controlling the pass device based on a quantity indicative of a current flowing through the second circuit path, and a switching circuit coupled to the second circuit path.

Abstract: A circuit for generating an output voltage, and regulating the output voltage to a target voltage, is described. The circuit comprises a pass device coupled between an input voltage level and an output voltage level, an error amplifier stage configured to generate a first control voltage on the basis of a reference voltage and the output voltage, a buffer stage configured to generate a drive signal for the pass device on the basis of the first control voltage, and a tracking circuit configured to track a voltage across the pass device and to generate a second control voltage on the basis of the voltage across the pass device. The buffer stage comprises a variable resistance element, for limiting a current flowing through the buffer stage on the basis of the second control voltage.

Abstract: A voltage regulator to provide a load current at an output node is presented. The voltage regulator has a pass transistor for providing the load current at the output node from an input node. The voltage regulator contains a driver stage to set a gate voltage at a gate of the pass transistor based on a drive voltage at a gate of a drive transistor. The voltage regulator has voltage regulation means to set the drive voltage in dependence of an indication of the output voltage at the output node and in dependence of a reference voltage for the output voltage. The driver stage has the drive transistor and a diode transistor, wherein the diode transistor forms a current mirror with the pass transistor. The driver stage has a current amplifier amplifies a drive current through the drive transistor to provide an amplified current through the diode transistor.

Abstract: A method is suggested for determining a state of a memory cell via a sense amplifier the method including applying a first signal to the sense amplifier; sensing a first response; determining a reference signal based on the first signal; sensing a second response based on a second signal that is determined based on the first signal; and determining the state of the memory cell based on the second response and the reference signal. Also, a memory device that is able to determine the state of the memory cell is provided.