Patents by Inventor Mihail Jefremow

Mihail Jefremow has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10459470
    Abstract: A digital voltage regulator and a method to regulate an output voltage at an output node based on an input voltage is presented. The regulator has a driver stage with N driver slices, with N>1. Each of the N driver slices can be activated or deactivated individually. A driver slice comprises a current source to provide an output current component to the output node, if the driver slice is activated. Furthermore, the regulator has a control unit to activate a number n of the N driver slices, based on a deviation of a feedback voltage from a reference voltage, where the feedback voltage is dependent on the output voltage.
    Type: Grant
    Filed: May 11, 2018
    Date of Patent: October 29, 2019
    Assignee: Dialog Semiconductor (UK) Limited
    Inventors: Mihail Jefremow, Dan Ciomaga, Gennadii Tatarchenkov, Stephan Drebinger, Fabio Rigoni, Alessandro Angeli, Petrus Hendrikus Seesink
  • Patent number: 10439421
    Abstract: A linear charger circuit and method for providing an output current at an output node is presented. The circuit contains a pass device connected between an input node and the output node, first and second replica devices connected in parallel to the pass device, with their control terminals coupled to a control terminal of the pass device. The first replica device is coupled to a first circuit path for determining whether current output by the linear charger circuit shall be terminated. The second replica device is coupled to a second circuit path for providing feedback for controlling the pass device, a control circuit coupled to the second circuit path for controlling the pass device based on a quantity indicative of a current flowing through the second circuit path, and a switching circuit coupled to the second circuit path.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: October 8, 2019
    Assignee: Dialog Semiconductor (UK) Limited
    Inventors: Mihail Jefremow, Selcuk Talay, Fabio Rigoni
  • Patent number: 10331152
    Abstract: A circuit for generating an output voltage, and regulating the output voltage to a target voltage, is described. The circuit comprises a pass device coupled between an input voltage level and an output voltage level, an error amplifier stage configured to generate a first control voltage on the basis of a reference voltage and the output voltage, a buffer stage configured to generate a drive signal for the pass device on the basis of the first control voltage, and a tracking circuit configured to track a voltage across the pass device and to generate a second control voltage on the basis of the voltage across the pass device. The buffer stage comprises a variable resistance element, for limiting a current flowing through the buffer stage on the basis of the second control voltage.
    Type: Grant
    Filed: April 6, 2018
    Date of Patent: June 25, 2019
    Assignee: Dialog Semiconductor (UK) Limited
    Inventors: Mihail Jefremow, Dan Ciomaga, Gennadii Tatarchenkov, Stephan Drebinger, Fabio Rigoni
  • Patent number: 10248145
    Abstract: A voltage regulator to provide a load current at an output node is presented. The voltage regulator has a pass transistor for providing the load current at the output node from an input node. The voltage regulator contains a driver stage to set a gate voltage at a gate of the pass transistor based on a drive voltage at a gate of a drive transistor. The voltage regulator has voltage regulation means to set the drive voltage in dependence of an indication of the output voltage at the output node and in dependence of a reference voltage for the output voltage. The driver stage has the drive transistor and a diode transistor, wherein the diode transistor forms a current mirror with the pass transistor. The driver stage has a current amplifier amplifies a drive current through the drive transistor to provide an amplified current through the diode transistor.
    Type: Grant
    Filed: February 21, 2018
    Date of Patent: April 2, 2019
    Assignee: Dialog Semiconductor (UK) Limited
    Inventors: Dan Ciomaga, Mihail Jefremow, Stephan Drebinger, Fabio Rigoni
  • Patent number: 10236041
    Abstract: A method is suggested for determining a state of a memory cell via a sense amplifier the method including applying a first signal to the sense amplifier; sensing a first response; determining a reference signal based on the first signal; sensing a second response based on a second signal that is determined based on the first signal; and determining the state of the memory cell based on the second response and the reference signal. Also, a memory device that is able to determine the state of the memory cell is provided.
    Type: Grant
    Filed: May 17, 2017
    Date of Patent: March 19, 2019
    Assignee: Infineon Technologies AG
    Inventors: Mihail Jefremow, Thomas Kern, Christian Peters
  • Publication number: 20190036353
    Abstract: A linear charger circuit and method for providing an output current at an output node is presented. The circuit contains a pass device connected between an input node and the output node, first and second replica devices connected in parallel to the pass device, with their control terminals coupled to a control terminal of the pass device. The first replica device is coupled to a first circuit path for determining whether current output by the linear charger circuit shall be terminated. The second replica device is coupled to a second circuit path for providing feedback for controlling the pass device, a control circuit coupled to the second circuit path for controlling the pass device based on a quantity indicative of a current flowing through the second circuit path, and a switching circuit coupled to the second circuit path.
    Type: Application
    Filed: July 31, 2017
    Publication date: January 31, 2019
    Inventors: Mihail Jefremow, Selcuk Talay, Fabio Rigoni
  • Patent number: 10152071
    Abstract: This application relates to a circuit for generating an output voltage and regulating the output voltage to a target voltage. The circuit includes a switchable voltage divider circuit configured to generate a feedback voltage that is a variable fraction of the output voltage, an error amplifier stage configured to generate a control voltage on the basis of a reference voltage and the variable fraction of the output voltage, a buffer stage configured to generate the output voltage on the basis of the control voltage, and a charge injection circuit configured to inject charge at an intermediate node between the error amplifier stage and the buffer stage to thereby modify the control voltage generated by the error amplifier stage. The application further relates to a method of operating such circuit.
    Type: Grant
    Filed: November 21, 2016
    Date of Patent: December 11, 2018
    Assignee: Dialog Semiconductor (UK) Limited
    Inventors: Dan Ciomaga, Mihail Jefremow, Stephan Drebinger, Fabio Rigoni
  • Publication number: 20180329440
    Abstract: A digital voltage regulator and a method to regulate an output voltage at an output node based on an input voltage is presented. The regulator has a driver stage with N driver slices, with N>1. Each of the N driver slices can be activated or deactivated individually. A driver slice comprises a current source to provide an output current component to the output node, if the driver slice is activated. Furthermore, the regulator has a control unit to activate a number n of the N driver slices, based on a deviation of a feedback voltage from a reference voltage, where the feedback voltage is dependent on the output voltage.
    Type: Application
    Filed: May 11, 2018
    Publication date: November 15, 2018
    Inventors: Mihail Jefremow, Dan Ciomaga, Gennadii Tatarchenkov, Stephan Drebinger, Fabio Rigoni, Alessandro Angeli, Petrus Hendrikus Seesink
  • Publication number: 20180292853
    Abstract: A circuit for generating an output voltage, and regulating the output voltage to a target voltage, is described. The circuit comprises a pass device coupled between an input voltage level and an output voltage level, an error amplifier stage configured to generate a first control voltage on the basis of a reference voltage and the output voltage, a buffer stage configured to generate a drive signal for the pass device on the basis of the first control voltage, and a tracking circuit configured to track a voltage across the pass device and to generate a second control voltage on the basis of the voltage across the pass device. The buffer stage comprises a variable resistance element, for limiting a current flowing through the buffer stage on the basis of the second control voltage.
    Type: Application
    Filed: April 6, 2018
    Publication date: October 11, 2018
    Inventors: Mihail Jefremow, Dan Ciomaga, Gennadii Tatarchenkov, Stephan Drebinger, Fabio Rigoni
  • Publication number: 20180239380
    Abstract: A voltage regulator to provide a load current at an output node is presented. The voltage regulator has a pass transistor for providing the load current at the output node from an input node. The voltage regulator contains a driver stage to set a gate voltage at a gate of the pass transistor based on a drive voltage at a gate of a drive transistor. The voltage regulator has voltage regulation means to set the drive voltage in dependence of an indication of the output voltage at the output node and in dependence of a reference voltage for the output voltage. The driver stage has the drive transistor and a diode transistor, wherein the diode transistor forms a current mirror with the pass transistor. The driver stage has a current amplifier amplifies a drive current through the drive transistor to provide an amplified current through the diode transistor.
    Type: Application
    Filed: February 21, 2018
    Publication date: August 23, 2018
    Inventors: Dan Ciomaga, Mihail Jefremow, Stephan Drebinger, Fabio Rigoni
  • Patent number: 10048710
    Abstract: A voltage regulator which provides at an output node a load current at an output voltage is described. The voltage regulator comprises a pass transistor for providing the load current at the output node from an input node, and a driver stage configured to set the gate voltage of the pass transistor based on a drive current. The voltage regulator has voltage regulation means to set the drive current in dependence of an indication of the output voltage at the output node and in dependence of a reference voltage for the output voltage. The voltage regulator has bypass regulation means to set the drive current in dependence of an indication of the gate-to-source voltage at the pass transistor and in dependence of a target voltage for the gate—to activate the voltage regulation means and/or the bypass regulation means. source voltage. The voltage regulator also comprises mode selection means.
    Type: Grant
    Filed: May 23, 2016
    Date of Patent: August 14, 2018
    Assignee: Dialog Semiconductor (UK) Limited
    Inventors: Mihail Jefremow, Dan Ciomaga, Marcus Weis, Stephan Drebinger, Fabio Rigoni
  • Publication number: 20180190333
    Abstract: A method is suggested for determining a state of a memory cell via a sense amplifier the method including applying a first signal to the sense amplifier; sensing a first response; determining a reference signal based on the first signal; sensing a second response based on a second signal that is determined based on the first signal; and determining the state of the memory cell based on the second response and the reference signal. Also, a memory device that is able to determine the state of the memory cell is provided.
    Type: Application
    Filed: May 17, 2017
    Publication date: July 5, 2018
    Inventors: Mihail Jefremow, Thomas Kern, Christian Peters
  • Patent number: 10001795
    Abstract: A linear regulator is presented. It comprises a first amplifier stage, one of the inputs being coupled with the output of the linear regulator. It has an intermediate amplifier stage. The input of the intermediate amplifier stage is coupled to the output of the first amplifier stage. It has a driver stage having a pass device driven by the output of the driver stage. The output of the pass device provides the output of the linear regulator. The regulator has a voltage-to-current feedback circuit coupled with the driver stage and the output of the first amplifier stage for regulating the output resistance of the first amplifier stage depending on load conditions of the linear regulator. The voltage-to-current feedback circuit has a transistor and a current limitation circuit to limit the regulation of the output resistance of the first amplifier stage to low load conditions of the linear regulator.
    Type: Grant
    Filed: August 26, 2016
    Date of Patent: June 19, 2018
    Assignee: Dialog Semiconductor (UK) Limited
    Inventors: Mihail Jefremow, Dan Ciomaga, Qiao Yang, Stephan Drebinger, Fabio Rigoni
  • Publication number: 20170269619
    Abstract: This application relates to a circuit for generating an output voltage and regulating the output voltage to a target voltage. The circuit includes a switchable voltage divider circuit configured to generate a feedback voltage that is a variable fraction of the output voltage, an error amplifier stage configured to generate a control voltage on the basis of a reference voltage and the variable fraction of the output voltage, a buffer stage configured to generate the output voltage on the basis of the control voltage, and a charge injection circuit configured to inject charge at an intermediate node between the error amplifier stage and the buffer stage to thereby modify the control voltage generated by the error amplifier stage. The application further relates to a method of operating such circuit.
    Type: Application
    Filed: November 21, 2016
    Publication date: September 21, 2017
    Inventors: Dan Ciomaga, Mihail Jefremow, Stephan Drebinger, Fabio Rigoni
  • Publication number: 20170205841
    Abstract: A voltage regulator which provides at an output node a load current at an output voltage is described. The voltage regulator comprises a pass transistor for providing the load current at the output node from an input node, and a driver stage configured to set the gate voltage of the pass transistor based on a drive current. The voltage regulator has voltage regulation means to set the drive current in dependence of an indication of the output voltage at the output node and in dependence of a reference voltage for the output voltage. The voltage regulator has bypass regulation means to set the drive current in dependence of an indication of the gate-to-source voltage at the pass transistor and in dependence of a target voltage for the gate—to activate the voltage regulation means and/or the bypass regulation means. source voltage.
    Type: Application
    Filed: May 23, 2016
    Publication date: July 20, 2017
    Inventors: Mihail Jefremow, Dan Ciomaga, Marcus Weis, Stephan Drebinger, Fabio Rigoni
  • Publication number: 20170060157
    Abstract: A linear regulator is presented. It comprises a first amplifier stage, one of the inputs being coupled with the output of the linear regulator. It has an intermediate amplifier stage. The input of the intermediate amplifier stage is coupled to the output of the first amplifier stage. It has a driver stage having a pass device driven by the output of the driver stage. The output of the pass device provides the output of the linear regulator. The regulator has a voltage-to-current feedback circuit coupled with the driver stage and the output of the first amplifier stage for regulating the output resistance of the first amplifier stage depending on load conditions of the linear regulator. The voltage-to-current feedback circuit has a transistor and a current limitation circuit to limit the regulation of the output resistance of the first amplifier stage to low load conditions of the linear regulator.
    Type: Application
    Filed: August 26, 2016
    Publication date: March 2, 2017
    Inventors: Mihail Jefremow, Dan Ciomaga, Qiao Yang, Stephan Drebinger, Fabio Rigoni
  • Patent number: 9524766
    Abstract: The invention relates to methods and systems for reading a memory cell and in particular, an STT MRAM. In one example, a system for reading a memory cell includes a sense path and an inverse path. A reference current is provided through the sense path and is sampled via a first sampling element in the sense path, and a cell current from the memory cell is provided through the inverse sense path and is sampled via a second sampling element in the inverse sense path. Subsequently, the memory cell is disconnected from the inverse sense path, the cell current is provided through the sense path, the reference source is disconnected from the sense path, and the reference current is provided through the inverse sense path. The output levels are then determined by the cell and reference currents working against the sampled reference and sampled cell currents.
    Type: Grant
    Filed: May 18, 2015
    Date of Patent: December 20, 2016
    Assignee: Infineon Technologies AG
    Inventors: David Mueller, Wolf Allers, Mihail Jefremow
  • Patent number: 9489994
    Abstract: A memory circuit including a memory cell configured to provide a charge, voltage, or current to an associated bit-line; a sense amplifier configured to sense the charge, voltage, or current on the bit-line; a word-line circuit configured to control a word-line of the memory cell; and a tracking circuit configured to track one or more conditions of the memory circuit and provide a timing control signal at an output operative to adaptively control the word-line circuit.
    Type: Grant
    Filed: February 2, 2016
    Date of Patent: November 8, 2016
    Assignee: Infineon Technologies AG
    Inventors: Mihail Jefremow, Ulrich Backhausen, Thomas Kern
  • Patent number: 9460759
    Abstract: A sense amplifier of a memory cell having a sense voltage generating circuit configured to generate a sense voltage; and a sensing circuit configured to compare a bitline voltage of the memory cell with the sense voltage, and to output a digital output signal indicating a content of the memory cell, wherein during a sense phase, the sensing circuit is decoupled from a voltage supply which charges a bitline capacitance during a precharge phase, and is coupled to and supplied by the bitline capacitance. The sense voltage generating circuit may be further configured to generate a sense voltage that during a precharge phase is dependent on the voltage supply and during a sense phase is independent of the voltage supply.
    Type: Grant
    Filed: January 7, 2014
    Date of Patent: October 4, 2016
    Assignee: Infineon Technologies AG
    Inventors: Thomas Kern, Mihail Jefremow
  • Publication number: 20160148662
    Abstract: A memory circuit including a memory cell configured to provide a charge, voltage, or current to an associated bit-line; a sense amplifier configured to sense the charge, voltage, or current on the bit-line; a word-line circuit configured to control a word-line of the memory cell; and a tracking circuit configured to track one or more conditions of the memory circuit and provide a timing control signal at an output operative to adaptively control the word-line circuit.
    Type: Application
    Filed: February 2, 2016
    Publication date: May 26, 2016
    Inventors: Mihail Jefremow, Ulrich Backhausen, Thomas Kern